IP Library Granted Patent US 7,567,194
Granted Patent B2
US 7,567,194 · App. 12/143,331 · Granted Jul 28, 2009

Delta sigma modulator and delta sigma A/D converter

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Quick Facts
Patent No.
US 7,567,194
App. No.
12/143,331
Granted
Jul 28, 2009
Kind
B2
Abstract

With a delta sigma modulator of this invention, a plurality of clocks required to control a switching circuit can be easily generated and correlation among phases of the plurality of clocks can be automatically maintained while a frequency of the clocks is modified. A ring oscillator is formed of three delay circuits provided with differential amplifiers in the delta sigma modulator. A clock producing circuit produces the plurality of clocks to control the switching circuit by delaying three-phase clocks outputted from the ring oscillator. All the tail currents Ic in the differential amplifiers in the delay circuits in the ring oscillator and the tail currents Ic in the differential amplifiers in the delay circuits in the clock producing circuit are proportional to each other.

Claims (13)

1. A delta sigma modulator comprising:

an integrator comprising a switching circuit;

a D/A converter that converts an output of the integrator into an analog output and feeds the analog output back to the integrator; and

a clock generation circuit comprising a ring oscillator comprising a plurality of first differential amplifiers connected to each other so as to generate a first set of clocks having phases different from each other and a plurality of second differential amplifiers delaying the first set of clocks generated by the first differential amplifiers so as to generate a second set of clocks,

wherein the switching circuit is configured to be controlled by the second set of clocks, and a plurality of tail currents flowing through the first differential amplifiers and the second differential amplifiers is configured to vary so as to maintain the same relative magnitudes among the tail currents.

2. The delta sigma modulator of claim 1 , further comprising a current source and a plurality of current mirror circuits, each of the current mirror circuits providing each of the first and second differential amplifiers with a tail current proportional to a current supplied from the current source, respectively.

3. A delta sigma A/D converter comprising:

an integrator comprising a switching circuit;

a D/A converter that converts an output of the integrator into an analog output and feeds the analog output back to the integrator;

a digital filter receiving the analog output; and

a clock generation circuit comprising a ring oscillator comprising a plurality of first differential amplifiers connected to each other so as to generate a first set of clocks having phases different from each other and a plurality of second differential amplifiers delaying the first set of clocks generated by the first differential amplifiers so as to generate a second set of clocks,

wherein the switching circuit is configured to be controlled by the second set of clocks, the digital filter is configured to be controlled by one of the second set of clocks, and a plurality of tail currents flowing through the first differential amplifiers and the second differential amplifiers is configured to vary so as to maintain the same relative magnitudes among the tail currents.

4. The delta sigma A/D converter of claim 3 , further comprising a current source and a plurality of current mirror circuits, each of the current mirror circuits providing each of the first and second differential amplifiers with a tail current proportional to a current supplied from the current source, respectively.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2008
From: HASEGAWA, KAZUO
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 021405/0877 →