Semiconductor device
View Patent ↗In the semiconductor device, a gate region is formed in a mesh pattern having first polygonal shapes and second polygonal shapes the area of which is smaller than that of the first polygonal shapes, and drain regions and source regions are disposed within the first polygonal shapes and the second polygonal shapes, respectively. With this configuration, the forward transfer admittance gm can be increased as compared with a structure in which gate regions are disposed in a stripe pattern. Furthermore, compared with a case in which a gate region is disposed in a grid pattern, deterioration in forward transfer characteristics (amplification characteristics) due to an increase in input capacitance Ciss can be minimized while a predetermined withstand voltage is maintained.
1. A semiconductor device comprising:
a semiconductor substrate of a first general conductivity type configured to operate as a back gate region;
a channel region of a second general conductivity type disposed on a front surface of the semiconductor substrate;
a gate region of the first general conductivity type formed in a surface portion of the channel region so as to form a mesh pattern comprising first mesh cells and second mesh cells, each of the first and second mesh cells surrounds a portion of the channel region, the first mesh cell being a first polygon and the second mesh cell being a second polygon that is smaller than the first polygon, each first mesh cell being disposed next to a corresponding second mesh cell, and the gate region being electrically connected to the back gate region;
a plurality of source regions formed in corresponding second mesh cells; and
a plurality of drain regions formed in corresponding first mesh cells,
wherein the source regions are separated from the gate region at least by a first distance, and the drain regions are separated from the gate region at least by a second distance that is larger than the first distance.
2. The semiconductor device of claim 1 , wherein each of the first mesh cells is in contact with at least two second mesh cells, and each of the second mesh cells is in contact with at least two first mesh cells.
3. The semiconductor device of claim 1 , wherein the first polygon comprises a first side and a second side shorter than the first side, and the first side is in contact with the second polygon and the second side is in contact with a second side of another first polygon.
4. The semiconductor device of claim 1 , wherein the first polygon is a octagon, and the second polygon is a square.
5. The semiconductor device of claim 1 , further comprising a drain electrode disposed on the front surface of the semiconductor substrate and connecting the drain regions, a source electrode disposed on the front surface of the semiconductor substrate and connecting the source regions, and a gate electrode disposed on a back surface of the semiconductor substrate so as to be connected to the back gate region.
6. The semiconductor device of claim 5 , wherein the drain electrode and the source electrode each have a comb shape.