Method of forming an at least penta-sided-channel type of FinFET transistor
An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.
1. A method of forming an at least penta-sided-channel type of FinFET transistor, the method comprising:
providing a base;
forming a fin on the base;
epitaxially growing a body of semiconductor material, which includes a channel region, on the base,
at least the channel region, in cross-section transverse to a long dimension of the body, having five or more planar surfaces above the base, wherein the five or more planar surfaces include at least two beveled surfaces and the at least two beveled surfaces exhibit at least one of a {1,1,1} surface and a {3,1,1} surface;
selectively doping the semiconductor body to produce, in the long dimension, source/drain regions sandwiching the channel region,
forming a gate insulator on the channel region of the body; and
forming a gate electrode formed on the gate insulator.
2. The method of claim 1 , wherein the epitaxially growing of the body includes:
varying materials of an atmosphere in which the epitaxial growth occurs in order to induce a strained semiconductor material in the body.
3. The method of claim 1 , wherein the epitaxially growing of the semiconductor body includes:
forming a semiconductor body with strain-inducing semiconductor material and strained semiconductor material on the fin.
4. The method of claim 1 , wherein the epitaxially growing of the semiconductor body includes:
forming the base with strain-inducing semiconductor material; and
forming the semiconductor body with strained semiconductor material on the fin.
5. The method of claim 1 , wherein:
the forming of the fin includes
providing a semiconductor substrate,
forming a mask on the semiconductor substrate,
forming trenches in the semiconductor substrate aside the mask to obtain an inverted T-shaped semiconductor structure having a horizontal portion and the fin extending perpendicularly therefrom;
the providing of the base includes
forming isolation structures that fill the trenches, and
removing the mask such that a recess remains relative to the isolation structures and located above the fin; and
the epitaxial growing of the body includes
starting the epitaixial growth on the fin,
filling the recess with the inchoate body, and
expanding the inchoate body out of the recess onto the isolation structures such that the five or more planar surfaces of the body are located above the isolation structures.
6. The method of claim 5 , wherein the providing of the base further includes:
forming sidewall spacers on the fin.
7. The method of claim 6 , wherein the providing the base further includes:
sizing the sidewall spacers such that at least a portion of the fin remains exposed to the recess.
8. The method of claim 1 , wherein:
the providing of the base includes
providing a semiconductor substrate,
forming a buried oxide (BOX) structure on the semiconductor substrate;
the forming of the fin includes locating the fin on the BOX structure; and
the epitaxial growing of the body includes
starting the epitaxial growth on the fin, and
expanding the inchoate body off the fin and onto the BOX structure such that the five or more planar surfaces of the body are located above the BOX structure.
9. The method of claim 1 , wherein:
the body is formed of silicon.
10. The method of claim 1 , wherein the epitaxially growing of the body includes:
varying a temperature at which the epitaixial growth occurs in order that the cross-section of the body includes at least seven planar surfaces.
11. The method of claim 10 , wherein:
the body is formed of silicon;
the body, in the cross-section, has at least seven planar surfaces;
the at least seven planar surfaces include at least four beveled surfaces;
the at least four beveled surfaces exhibit both of the {1,1,1} and {3,1,1} surfaces.
12. The method of claim 11 , wherein adjacent beveled surfaces alternate between being the {1,1,1} surface and the {3,1,1} surface.
13. The method of claim 1 , wherein the base includes,
a base semiconductor structure having a fin extending perpendicularly therefrom and shoulder portions above which the fin extends, and
one or more isolation regions formed on the base semiconductor structure, the one or more isolation regions extending above the fin so as to define a recess in the one or more isolation regions above the fin.
14. The method of claim 13 , wherein the semiconductor body has a stalk portion extending down into and at least partially filling the recess.
15. The FinFET transistor of claim 14 , wherein the stalk portion of the body has at least five planar surfaces above the base, at least two of the planar surfaces being beveled surfaces.
16. The method of claim 1 , wherein the channel region has at least five planar surfaces above the base, at least two of the planar surfaces being beveled surfaces.