IP Library Granted Patent US 7,671,436
Granted Patent B2
US 7,671,436 · App. 12/151,108 · Granted Mar 2, 2010

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Quick Facts
Patent No.
US 7,671,436
App. No.
12/151,108
Granted
Mar 2, 2010
Kind
B2
Abstract

Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.

Claims (21)

1. An assembly comprising an integrated circuit die having pads and an external body having pads, said die electrically connected to said body by conducting regions between said pads of said die and said pads of said body characterized in that a compliant region underlies at least 75% of a surface area of said pads of said die that are critical pads or at least 75% of a surface area of said pads of said body that are critical pads wherein said compliant region has an average thickness of at least 10 μm, has a modulus less than or equal to 250 MPa, and has an elongation to failure greater than or equal to 75%.

2. The assembly of claim 1 wherein said modulus is less than 200 MPa.

3. The assembly of claim 1 wherein said modulus is less than 100 MPa.

4. The assembly of claim 1 wherein said elongation to failure is greater than 100%.

5. The assembly of claim 4 wherein said elongation to failure is greater than 500%.

6. The assembly of claim 1 wherein at least 85% of said surface area is underlain.

7. The assembly of claim 6 wherein at least 95% of said surface area is underlain.

8. An integrated circuit comprising a die including pads to which external electrical connection is made characterized in that a compliant region underlies at least 75% of a surface area of said pads that are critical pads wherein said compliant region has an average thickness of at least 10 μm, has a modulus less than or equal to 250 MPa, and has an elongation to failure of greater than or equal to 75%.

9. The integrated circuit of claim 8 wherein said modulus is less than 200 MPa.

10. The integrated circuit of claim 9 wherein said modulus is less than 100 MPa.

11. The integrated circuit of claim 8 wherein said elongation to failure is greater than 100%.

12. The integrated circuit of claim 11 wherein said elongated failure is greater than 500%.

13. The integrated circuit of claim 8 wherein at least 85% of said surface area is underlain.

14. The integrated circuit of claim 13 wherein at least 95% of said surface area is underlain.

15. A circuit board including pads suitable for electrical connection to an electronic device characterized in that a compliant region underlies at least 75% of a surface area of said pads that are critical pads wherein said compliant region has an average thickness of at least 10 μm, has a modulus less than or equal to 250 MPa, and has an elongation to failure of greater than or equal to 75%.

16. The circuit board of claim 15 wherein said modulus is less than 200 MPa.

17. The circuit board of claim 16 wherein said modulus is less than 100 MPa.

18. The circuit board of claim 15 wherein said elongation to failure is greater than 100%.

19. The circuit board of claim 18 wherein said elongation to failure is greater than 500%.

20. The circuit board of claim 15 wherein at least 85% of said surface area is underlain.

21. The circuit board of claim 20 wherein at least 95% of said surface area is underlain.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2008
From: AMIN, AHMED NUR; BACHMAN, MARK ADAM; CROUTHAMEL, DAVID LEE; OSENBACH, JOHN WILLIAM; VACCARO, BRIAN THOMAS
To: AGERE SYSTEMS INC.
Reel/Frame 021031/0832 →