Semiconductor device having multiple I/O modes
View Patent ↗Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to input modes and a data detector configured to detect the data in response to the data strobe signal output from the phase controller.
1. A semiconductor device, comprising:
a data buffer configured to receive data;
a strobe input buffer configured to receive a data strobe signal;
a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to input modes; and
a data detector configured to detect the data in response to the data strobe signal output from the phase controller.
2. The semiconductor device as recited in claim 1 , wherein the phase controller comprises one or more delays delaying the data strobe signal by a predetermined number of degrees.
3. The semiconductor device as recited in claim 2 , wherein the one or more delays comprise one or more voltage controlled delay lines connected in series.
4. The semiconductor device as recited in claim 3 , wherein the one or more voltage controlled delay lines comprise a phase locked loop further comprising a voltage controlled oscillator and the one or more voltage controlled delay lines are configured to be controlled by a control voltage controlling the voltage controlled oscillator.
5. The semiconductor device as recited in claim 1 , wherein the input modes are determined by external signals or internal signals of the semiconductor device.
6. The semiconductor device as recited in claim 1 , wherein the phase controller is configured to shift a phase of the data strobe signal by 0 degrees, 60 degrees, and 90 degrees according to the input modes.
7. A semiconductor device, comprising;
an output driver configured to output data;
a phase locked loop configured to output clocks having different phases;
a selector configured to select one of the clocks as a data strobe signal; and
a strobe output buffer configured to output the selected data strobe signal to an outside of a chip.
8. The semiconductor device as recited in claim 7 , wherein the phase locked loop further comprises a voltage controlled oscillator and the clocks are output from different output terminals of the voltage controlled oscillator.
9. A semiconductor device, comprising;
a data buffer configured to receive data;
a strobe input buffer configured to receive an input data strobe signal;
a phase controller configured to shift a phase of the input data strobe signal by different numbers of degrees, including 0 degrees, according to input modes or to delay a phase of an output data strobe signal by different phases, including 0 degrees, according to output modes;
a data detector configured to detect the data in response to the input strobe signal output from the input phase controller;
an output driver configured to output data; and
a strobe output buffer configured to output the output data strobe signal output from the phase controller to an outside of a chip.
10. The semiconductor device as recited in claim 9 , wherein the input modes are determined by external signals or internal signals of the semiconductor device.
11. The semiconductor device as recited in claim 9 , wherein the output modes are determined by external signals or internal signals of the semiconductor device.
12. A semiconductor device, comprising;
a data buffer configured to receive data;
a strobe input buffer configured to receive an input data strobe signal;
an input phase controller configured to shift a phase of the input data strobe signal by different numbers of degrees, including 0 degrees, according to input modes;
a data detector configured to detect the data in response to the input data strobe signal output from the input phase controller;
an output driver configured to output data;
a phase locked loop configured to output clocks having different phases;
a selector configured to select one of the clocks as a data strobe signal according to output modes; and
a strobe output buffer configured to output the selected data strobe signal to an outside of a chip.
13. The semiconductor device as recited in claim 12 , wherein the input modes are determined by external signals or internal signals of the semiconductor device.
14. The semiconductor device as recited in claim 12 , wherein the output modes are determined by external signals or internal signals of the semiconductor device.