Semiconductor memory device removing parasitic coupling capacitance between word lines

1. A semiconductor memory device comprising:

a plurality of main word lines shared by a plurality of mats, each mat comprising a plurality of sub word lines, wherein the plurality of sub word lines are sequentially arranged;

a decoding unit decoding a row address bit to output a word line driving signal,

a plurality of sub word line driving units each configured to activate one of the sub word lines in response to the word line driving signal, wherein the neighboring sub word lines of the plurality of sub word lines are non-sequentially activated so as to correspond with the word line driving signal, and

wherein neighboring sub word line driving units of the plurality of sub word line driving units are connected to different main word lines,

wherein even sub world line driving units of the plurality of sub word line driving units are arranged in the same column, and odd sub word line driving units of the plurality of sub word line driving units are arranged in the same column,

wherein a notation of the plurality of sub word line driving units are not matched to a notation of the plurality of sub word lines connected to the plurality of sub word line driving units, respectively.

2. The semiconductor memory device according to claim 1 , wherein the sub word line driving units are disposed in pairs and the sub word lines are arranged in an lattice pattern between the mats.

3. The semiconductor memory device according to claim 2 , wherein paired sub word line driving units disposed to be adjacent to each other in a row direction are connected to different main word lines.

4. The semiconductor memory device according to claim 2 , wherein paired sub word line driving units disposed to be adjacent to each other in a column direction are connected to different main word lines.

5. The semiconductor memory device according to claim 1 , wherein the decoding unit comprises:

a logic operation unit performing a logical operation on a plurality of row address bits;

a plurality of selecting units, each selecting unit selectively controlling output signals of the logic operation unit according to a first row address bit; and

a driving unit driving an output signal of the selecting unit and outputting a plurality of word line driving signals.

6. The semiconductor memory device according to claim 5 , wherein the first row address bit has a lowest bit.

7. The semiconductor memory device according to claim 5 , wherein the first row address bit is an address for selecting the main word line.

8. The semiconductor memory device according to claim 5 , wherein the plurality of row address bits includes a second row address bit, a third row address bit, and a fourth row address bit having the lowest bit addresses except the first row address bit.

9. The semiconductor memory device according to claim 5 , wherein each selecting unit comprises:

a first selecting unit portion selectively outputting a first output signal received from the logic operation unit according to a logic state of the first row address bit; and

a second selecting unit portion selectively outputting a second output signal received from the logic operation unit according to a logic state of the first row address bit.

10. The semiconductor memory device according to claim 9 , wherein the first selecting unit portion comprises:

a first transmission gate outputting the first output signal as a second word line driving signal in activation of the first row address bit; and

a second transmission gate outputting the first output signal as a first word line driving signal in inactivation of the first row address bit.

11. The semiconductor memory device according to claim 9 , wherein the second selecting unit comprises:

a third transmission gate outputting the second output signal as the first word line driving signal in activation of the first row address bit; and

a fourth transmission gate outputting the second output signal as the second word line driving signal in inactivation of the first row address bit.

12. A semiconductor memory device comprising:

a first main word line;

a second main word line;

wherein the first main word line and the second main word line are shared by a plurality of mats;

a first sub word line driving unit connected to the first main word line and driving a first sub word line according to a first word line driving signal; and

a second sub word line driving unit connected to the second main word line and driving a second sub word line according to a second word line driving signal; and

a decoding unit decoding a row address bit and outputting the first word line driving signal and the second word line driving signal,

wherein the first sub word line driving unit is arranged adjacent to the second sub word line driving unit, and

wherein the first sub word line and the second sub word line are sequentially arranged, the first sub word line and the second sub word line are non-sequentially activated, so as to correspond with the first word line driving signal and the second word line driving signal,

wherein a notation of the first sub word line driving unit and a notation of the second sub word line driving unit are not matched to a notation of the first sub word line and a notation of the second sub word line connected to the first sub word line driving unit and the second sub word line driving unit, respectively.

13. The semiconductor memory device according to claim 12 , wherein the decoding unit comprises:

a plurality of logic operation units performing a logical operation on a plurality of row address bits;

a plurality of selecting unit selectively controlling output signals of the logic operation unit according to a first row address bit; and

a driving unit driving an output signal of the selecting unit and outputting a plurality of word line driving signals.

14. The semiconductor device according to claim 13 , wherein the first row address bit has a lowest bit.

15. The semiconductor device according to claim 13 , wherein the first row address bit is an address for selecting one of the first main word line and the second main word line.

16. The semiconductor device according to claim 13 , wherein the plurality of row address bits includes a second row address bit, a third row address bit, and a fourth row address bit having the lowest bit addresses except the first row address bit.

17. The semiconductor memory device according to claim 13 , wherein each selecting unit includes:

a first selecting unit portion selectively outputting a first output signal received from the logic operation unit according to a logic state of the first row address bit; and

a second selecting unit portion selectively outputting a second output signal received from the logic operation unit according to a logic state of the first row address bit.

18. The semiconductor memory device according to claim 17 , wherein the first selecting unit portion comprises:

a first transmission gate outputting the first output signal as a second word line driving signal in activation of the first row address bit; and

a second transmission gate outputting the first output signal as a first word line driving signal in inactivation of the first row address bit.

19. The semiconductor memory device according to claim 17 , wherein the second selecting unit portion includes:

a third transmission gate ting output the second output signal as the first word line driving signal in activation of the first row address bit; and

a fourth transmission gate outputting the second output signal as the second word line driving signal in inactivation of the first row address bit.