IP Library Granted Patent US 8,239,434
Granted Patent B2
US 8,239,434 · App. 12/170,334 · Granted Aug 7, 2012

System, method, and apparatus for distortion analysis

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Quick Facts
Patent No.
US 8,239,434
App. No.
12/170,334
Granted
Aug 7, 2012
Kind
B2
Abstract

A system, method, and apparatus for distortion analysis is provided. A method in accordance with at least one embodiment of the present disclosure may include receiving a clock frequency at a direct digital synthesizer (DDS) and generating at least one stream of phase numbers via said DDS. The method may further include generating a digital sine wave using, at least in part, said clock frequency and said at least one stream of phase numbers. Of course, additional implementations are also within the scope of the present disclosure.

Claims (25)

1. A method comprising:

receiving a clock frequency at a direct digital synthesizer (DDS);

generating at least one stream of phase numbers at said DDS;

generating a digital sine wave using, at least in part, said clock frequency and said at least one stream of phase numbers; and

canceling at least one harmonic associated with said digital sine wave to generate a digital distortion correction output.

2. The method of claim 1 wherein said at least one stream of phase numbers is generated by a phase accumulator associated with said DDS.

3. The method of claim 1 further comprising receiving said digital sine wave at a first digital-to-analog (DAC) converter.

4. The method of claim 3 further comprising generating, at said first DAC, an analog output approximating an analog sine wave.

5. The method of claim 1 further comprising receiving said digital distortion correction output from said DDS at a second digital-to-analog converter (DAC) and generating an analog distortion correction output.

6. The method of claim 5 further comprising combining an analog output and said analog distortion correction output to generate a composite output for transmission to a circuit-under-test.

7. An apparatus comprising:

distortion analysis circuitry configured to receive a clock frequency at a direct digital synthesizer (DDS) included within the distortion analysis circuitry, said distortion analysis circuitry further configured to generate at least one stream of phase numbers at said DDS, said DDS further configured to generate a digital sine wave using, at least in part, said clock frequency and said at least one stream of phase numbers, wherein said distortion analysis circuitry is further configured to cancel at least one harmonic associated with said digital sine wave to generate a digital distortion correction output.

8. The apparatus according to claim 7 wherein said at least one stream of phase numbers is generated by a phase accumulator associated with said DDS.

9. The apparatus according to claim 7 wherein said distortion analysis circuitry is further configured to receive said digital sine wave at a first digital-to-analog converter (DAC).

10. The apparatus according to claim 9 wherein said distortion analysis circuitry is further configured to generate, at said first DAC, an analog output approximating an analog sine wave.

11. The apparatus according to claim 9 wherein said distortion analysis circuitry is further configured to receive said digital distortion correction output from said DDS at a second digital-to-analog converter (DAC) and to generate an analog distortion correction output.

12. The apparatus according to claim 11 wherein said distortion analysis circuitry is further configured to combine said analog output and said analog distortion correction output to generate a composite output for transmission to a circuit-under-test.

13. A distortion analysis system comprising:

phase accumulator circuitry configured to generate at least one stream of numbers;

a direct digital synthesizer (DDS) included within a distortion analysis circuitry, the DDS being configured to receive a clock frequency, said DDS being configured to generate a digital sine wave using, at least in part, said clock frequency and said at least one stream of phase numbers, wherein said DDS is further configured to cancel at least one harmonic associated with said digital sine wave to generate a digital distortion correction output; and

differential amplifier circuitry, included within the distortion analysis circuitry, the differential amplifier circuitry being configured to receive an output signal from circuitry under test and an input signal to the circuitry under test, said differential amplifier circuitry is configured to generate a differential amplifier output.

14. The distortion analysis system according to claim 13 further comprising a first digital-to-analog converter (DAC) configured to receive said digital sine wave.

15. The distortion analysis system according to claim 14 wherein said first DAC is configured to generate an analog output approximating an analog sine wave.

16. The distortion analysis system according to claim 14 further comprising a second digital-to-analog converter (DAC) configured to receive said digital distortion correction output from said DDS and to generate a distortion correction output.

17. The distortion analysis system according to claim 16 wherein said analog output and said distortion correction output are combined to generate a composite output for transmission to a circuit-under-test.

Assignments (10)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 047185, FRAME 0624 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: XCERRA CORPORATION
Reel/Frame 066762/0811 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047185 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 28, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047675/0354 →
PATENT SECURITY AGREEMENT Recorded Oct 2, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047185/0624 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7261561 AND REPLACE WITH PATENT NUMBER 7231561 PREVIOUSLY RECORDED ON REEL 034660 FRAME 0188. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Feb 11, 2016
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 037824/0372 →
RELEASE OF SECURITY INTEREST IN UNITED STATES PATENTS Recorded Dec 18, 2014
From: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
To: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
Reel/Frame 034660/0394 →
SECURITY AGREEMENT Recorded Dec 18, 2014
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 034660/0188 →
CHANGE OF NAME Recorded May 27, 2014
From: LTX-CREDENCE CORPORATION
To: XCERRA CORPORATION
Reel/Frame 033032/0768 →
SECURITY AGREEMENT Recorded Jan 17, 2014
From: LTX-CREDENCE CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 032086/0476 →
MERGER Recorded Mar 3, 2011
From: CREDENCE SYSTEMS CORPORATION
To: LTX-CREDENCE CORPORATION
Reel/Frame 025894/0629 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2008
From: MAX, SOLOMON; HANNAFORD, CHRISTOPHER JOEL
To: LTX CORPORATION
Reel/Frame 021782/0460 →