Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making
View Patent ↗Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.
1. A semiconductor device comprising:
a substrate layer of a semiconductor material of a first conductivity type;
a first layer of a semiconductor material of the first conductivity type on the substrate layer, the first layer having a surface opposite the substrate layer;
one or more channel regions of a semiconductor material of the first conductivity type on the surface of the first layer, the one or more channel regions comprising an upper surface and first and second sidewalls;
gate regions of a semiconductor material of a second conductivity type different than the first conductivity type on the first and second sidewalls of the one or more channel regions and on the upper surface of the first layer adjacent to the one or more channel regions, wherein the one or more channel regions and the gate regions on the first and second sidewalls of the one or more channel regions form a raised region having sidewalls comprising the gate regions, wherein the sidewalls of the raised region are tapered such that the raised region is narrower near the upper surface of the channel region than adjacent the first layer; and
a third layer of a semiconductor material of the first conductivity type on the upper surface of the raised region;
wherein each of the one or more channel regions has a dopant concentration of 5×10 16 to 1×10 18 cm −3 ;
wherein the distance between the upper surface of the raised region and the surface of the first layer is 0.1 to 2 μm; and
wherein the minimum distance between the first and second sidewalls of each of the one or more channel regions in a direction parallel to the upper surface of the channel regions is 0.1 to 0.5 μm.
2. The semiconductor device of claim 1 , wherein the first layer of semiconductor material of the first conductivity type has a thickness of 5 to 15 μm and a doping concentration of 4×10 15 to 2×10 16 cm −3 .
3. The semiconductor device of claim 1 , wherein the substrate has a thickness of 100 to 500 μm and a doping concentration of 1×10 19 to 5×10 19 cm −3 .
4. The semiconductor device of claim 1 , wherein the third layer of semiconductor material of the first conductivity type has a thickness of 0.1 to 1.0 μm and a doping concentration of 1×10 19 to 1×10 20 cm −3 .
5. The semiconductor device of claim 1 , wherein the semiconductor material of the second conductivity type has a doping concentration of 5×10 18 to 1×10 20 cm −3 .
6. The semiconductor device of claim 1 , further comprising a fourth layer of a semiconductor material of the first conductivity type between the substrate and the first layer.
7. The semiconductor device of claim 6 , wherein the fourth layer of semiconductor material of the first conductivity type has a thickness of 0.1 to 1.0 μm and a doping concentration of 5×10 17 to 5×10 18 cm −3 .
8. The semiconductor device of claim 1 , wherein the device comprises a plurality of raised regions, wherein the plurality of raised regions are elongate and are arranged in spaced relationship as fingers.
9. The semiconductor device of claim 1 , wherein the semiconductor material of the first conductivity type is an n-type semiconductor material and wherein the semiconductor material of the second conductivity type is a p-type semiconductor material.
10. The semiconductor device of claim 1 , wherein the semiconductor material is a wide band-gap semiconductor material.
11. The semiconductor device of claim 1 , wherein the semiconductor material is SiC.
12. The semiconductor device of claim 1 , wherein the device is a Junction Field-Effect Transistor (JFET), a Static Induction Transistor (SIT), a Junction Field Effect Thyristor, or a JFET current limiter.
13. The device of claim 1 , wherein the device exhibits non-punch through behavior at an applied electric field of 2.4 MV/cm or less.
14. The semiconductor device of claim 1 , further comprising:
a first gate contact on the gate region on the first sidewall of the raised region and on the upper surface of the first layer adjacent to the first sidewall;
a second gate contact on the gate region on the second sidewall of the raised region and on the upper surface of the first layer adjacent to the second sidewall;
a source contact on the third layer; and
a drain contact on the substrate layer opposite the first layer.
15. A circuit comprising the semiconductor device of claim 14 .
16. The circuit of claim 15 , wherein the first and second gate contacts are electrically coupled.
17. The circuit of claim 15 , wherein the first and second gate contacts are not electrically coupled.
18. A circuit comprising first and second semiconductor devices as set forth in claim 14 , wherein the source contact of the first device is electrically coupled to a gate contact of the second device.
19. The circuit of claim 15 , wherein the circuit is an integrated circuit.