Flip chip semiconductor device having workpiece adhesion promoter layer for improved underfill adhesion
A semiconductor device assembly ( 200 ) includes a workpiece ( 205 ) having a surface including a die attach region corresponding to regions under an integrated circuit (IC) die 210 . The die attach region of workpiece ( 205 ) includes non-noble metal surfaces ( 215 ) and a plurality of flip chip (PC) pads at pad locations ( 214 ). A solder mask layer ( 207 ) is on a surface of the workpiece ( 205 ) outside the die attach region. The non-noble metal surfaces ( 215 ) in the die attach region include an adhesion promoter layer ( 221 ), wherein the adhesion promoter layer 221 is absent from the plurality of PC pads ( 214 ). An integrated circuit (IC) die ( 210 ) having a plurality of bumps ( 211 ) bonded in a flip chip arrangement to the workpiece ( 205 ). An underfill material ( 232 ) fills a space between the bumped IC die ( 210 ) and the workpiece ( 205 ).
1. A flip chip method for assembling an integrated circuit (IC) die having a plurality of bumps to a workpiece having a surface including a die attach region comprising non-noble metal surfaces and a plurality of flip chip (FC) pads at pad locations, comprising:
forming a solder mask layer on said surface of said workpiece, wherein said solder mask layer is excluded from said die attach region;
forming a metal comprising layer on said plurality of FC pads;
forming an adhesion promoter layer on said non-noble metal surfaces, but not on said plurality of FC pads;
attaching said bumped IC die in a FC arrangement to said workpiece, and
filling a space between said bumped semiconductor die and said workpiece with an underfill material.
2. The method of claim 1 , wherein said plurality of bumps comprise a noble metal, and wherein said forming a metal comprising layer step comprises selectively forming a layer comprising a noble metal on said plurality of FC pads, but not on said non-noble metal surfaces.
3. The method of claim 2 , wherein said forming an adhesion promoter layer comprises etching followed by a chemical conversion process to convert said non-noble surfaces to an organo-metallic layer.
4. The method of claim 1 , wherein said non-noble metal surfaces comprises Cu.
5. The method of claim 2 , wherein said attaching comprises ultrasonic bonding.
6. The method of claim 1 , wherein said workpiece comprises a dielectric or ceramic substrate.
7. The method of claim 1 , wherein said workpiece comprises a second IC die.
8. The method of claim 1 , wherein said adhesion promoter layer comprises a roughened surface.
9. The method of claim 8 , wherein said roughened surface comprises an organometallic copper oxide comprising layer.
10. A flip chip method for assembling an integrated circuit (IC) die having a plurality of noble metal comprising bumps to a workpiece having a surface including a die attach region comprising non-noble metal surfaces and a plurality of flip chip (FC) pads at pad locations, comprising:
forming a solder mask layer onto said surface of said workpiece, wherein said solder mask layer is excluded from said die attach region;
selectively forming a noble metal comprising layer on said plurality of FC pads;
processing said workpiece under conditions to provide an adhesion promoter layer onto said non-noble metal surfaces, wherein said noble metal comprising layer on said plurality of FC pads remains unreacted by said processing;
ultrasonically attaching said IC die in a Fe arrangement to said workpiece, and
filling a space between said IC die and said workpiece with an underfill material.
11. A semiconductor device assembly, comprising:
a workpiece having a surface including a die attach region comprising non-noble metal surfaces and a plurality of flip chip (FC) pads at pad locations, a solder mask layer on a surface of said workpiece, wherein said solder mask layer is excluded from said die attach re-ion, wherein said non-noble metal surfaces in said die attach region include an adhesion promoter layer, said adhesion promoter layer absent from said plurality of FC pads;
an integrated circuit (IC) die having a plurality of bumps bonded in a flip chip arrangement to said workpiece, and
an underfill material filling a space between said bumped IC die and said workpiece.
12. The semiconductor device assembly of claim 11 , wherein said plurality of bumps comprise a noble metal, and said plurality of FC pads comprise a noble metal.
13. The semiconductor device assembly of claim 12 , wherein said noble metal for said bumps and said noble metal for said plurality of FC pads comprise gold.
14. The semiconductor device assembly of claim 11 , wherein said non-noble metal surfaces comprises Cu.
15. The semiconductor device assembly of claim 14 , said adhesion promoter layer comprises a roughened surface.
16. The semiconductor device assembly of claim 15 , wherein said roughened surface comprises an organometallic copper oxide comprising layer.
17. The semiconductor device assembly of claim 11 , wherein said semiconductor device assembly comprises a chip scale package (CSP).
18. The semiconductor device assembly of claim 11 , wherein said semiconductor device assembly comprises a package on package (POP).