Bulk voltage detector
View Patent ↗A bulk voltage detector comprises a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal having a voltage gain that is increased within a predetermined voltage range around the target level, and an amplifier coupled with the voltage sensor, the amplifier configured to receive the first detection signal and invert and amplify the first detection signal.
1. A bulk voltage detector comprising:
a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal having a voltage gain that is increased when the bulk voltage has a value close to the target level; and
an amplifier coupled with the voltage sensor, the amplifier configured to receive the first detection signal and invert and amplify the first detection signal,
wherein the voltage sensor includes:
a control unit configured to determine activation of the voltage sensor;
a voltage dividing unit coupled with the control unit, the voltage dividing unit configured to be controlled by the control unit and provide the first detection signal by sensing the bulk voltage; and
a voltage gain adjusting unit that is connected to the voltage dividing unit and configured to control a voltage gain of the first detection signal.
2. The bulk voltage detector of claim 1 , wherein the voltage dividing unit includes:
a first dividing unit configured to receive an internal voltage, dropped and adjusted from an external supply voltage, and control a potential level of the first detection signal by dividing the internal voltage at a resistance ratio in response to ground power; and
a second dividing unit configured to control the potential level of the first detection signal at the resistance ratio in response to the bulk voltage.
3. The bulk voltage detector of claim 2 , wherein the first dividing unit and the second dividing unit include a plurality of PMOS transistors connected to each other in series.
4. The bulk voltage detector of claim 3 , wherein the voltage gain adjusting unit includes an NMOS transistor that is connected between the first dividing unit and the second dividing unit.
5. The bulk voltage detector of claim 4 , wherein the voltage gain adjusting unit is controlled so that an operation area is changed corresponding to the fluctuations of a voltage between a gate and a source of the NMOS transistor to control a voltage gain of an output node.
6. The bulk voltage detector of claim 5 , wherein the source of the NMOS transistor is connected to the second dividing unit, the gate of the NMOS transistor is connected to the first dividing unit, and a drain of the NMOS transistor is connected to the output node.
7. The bulk voltage detector of claim 1 , wherein the amplifier includes:
a first inversion unit configured to provide a second detection signal by inverting and amplifying the first detection signal; and
a second inversion unit coupled with the first inversion unit, the second inversion unit configured to invert and amplify the second detection signal.
8. A bulk voltage detector comprising:
a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal; and
an amplifier coupled with the voltage sensor, the amplifier configured to receive the first detection signal and invert and amplify the first signal,
wherein the voltage sensor includes a voltage gain adjusting unit that increases a voltage gain of the first detection signal when the bulk voltage is substantially the same as the target level;
wherein the voltage sensor includes:
a control unit configured to activate the voltage sensor;
a voltage dividing unit configured to be controlled by the control unit and provide the first detection signal by sensing the bulk voltage; and
a voltage gain adjusting unit that is connected to the voltage dividing unit and controls a voltage gain of the first detection signal.
9. The bulk voltage detector of claim 8 , wherein the voltage dividing unit includes:
a first dividing unit configured to receive an internal voltage, dropped and adjusted from an external supply voltage, and control a potential level of the first detection signal by dividing the internal voltage at a resistance ratio in response to ground power; and
a second dividing unit configured to control the potential level of the first detection signal at the resistance ratio in response to the bulk voltage.
10. The bulk voltage detector of claim 9 , wherein the first dividing unit and the second dividing unit include a plurality of PMOS transistors connected to each other in series.
11. The bulk voltage detector of claim 10 , wherein the voltage gain adjusting unit includes an NMOS transistor that is connected between the first dividing unit and the second dividing unit.
12. The bulk voltage detector of claim 11 , wherein the voltage gain adjusting unit is controlled so that an operation area is changed corresponding to the fluctuation of a voltage between a gate and a source of the NMOS transistor to control a voltage gain of the output node.
13. The bulk voltage detector of claim 12 , wherein the source of the NMOS transistor is connected to the second dividing unit, the gate of the NMOS transistor is connected to the first dividing unit, and a drain of the NMOS transistor is connected to the output node.
14. The bulk voltage detector of claim 8 , wherein the amplifier includes:
a first inversion unit configured to provide a second detection signal by inverting and amplifying the first detection signal; and
a second inversion unit coupled with the first inversion unit, the second inversion unit configured to invert and amplify the second detection signal.