IP Library Granted Patent US 8,151,456
Granted Patent B2
US 8,151,456 · App. 12/175,732 · Granted Apr 10, 2012

Method of producing substrate

Assignee: Fujitsu Limited
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,151,456
App. No.
12/175,732
Granted
Apr 10, 2012
Kind
B2
Abstract

The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.

Claims (22)

1. A method of producing a core substrate, comprising:

forming a pilot hole in a base member, the base member including a core section composed of carbon fiber-reinforced plastic, copper foils being bonded on both surfaces of the core section with prepregs;

coating an inner face of the pilot hole with a plated layer by electroless-plating;

electrolytic-plating the base member subsequent to the electroless-plating of the inner face of the pilot hole;

filling the pilot hole, whose inner face has been coated with the plated layer, with an insulating material composed of resin;

forming resist patterns, which coat planar areas of the pilot hole and edges of the pilot hole with a prescribed width, on both surfaces of the base member by laminating photoresist thereon and exposing and developing the photoresist;

forming copper foil patterns along the edges of the pilot hole and exposing the prepregs in both surfaces of the core section by etching the copper foils with using the resist patterns as masks;

removing the resist patterns;

integrating cable layers with the base member by successively placing a first additional prepreg, a cable sheet, in which cable patterns are formed on both surfaces of an insulating sheet, a second additional prepreg, and an additional copper foil, on each of the surfaces of the base member, and pressurizing and heating the cable layers to thermally cure the first additional prepregs and the second additional prepregs;

coaxially forming a through-hole, whose diameter is smaller than that of the pilot hole and that penetrates the cable layers and the base member, with the pilot hole so as to expose the insulating material as an inner face;

forming a plated through-hole on the inner face of the through-hole by electroless copper plating and electrolytic copper plating;

filling the through-hole with resin; and

etching the additional copper foils so as to form additional cable patterns on the both surfaces of the base member.

2. The method according to claim 1 ,

wherein an insulating film is formed on the plated layer, which has been formed on the inner face of the pilot hole, by an electrodeposition method using the plated layer as an electric power feeding layer, the forming of the insulating layer being performed subsequent to the electrolytic-plating of the base member and prior to the filing of the pilot hole.

3. The method according to claim 1 ,

wherein both surfaces of the base member are electroless-copper-plated after the filing of the pilot hole so as to coat both surfaces of the base member with electroless copper plated layers.

4. A method of producing a circuit board, comprising:

producing a core substrate according to the method of claim 1 ; and

laminating cable layers on both surfaces of the core substrate.

5. The method according to claim 4 ,

wherein the cable layers are formed by build-up method.

Assignments (3)
CHANGE OF NAME Recorded Jun 6, 2023
From: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
To: FICT LIMITED
Reel/Frame 063881/0638 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2020
From: FUJITSU LIMITED
To: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
Reel/Frame 052345/0603 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2008
From: MAEHARA, YASUTOMO; IIDA, KENJI; ABE, TOMOYUKI; HIRANO, SHIN; NAKAGAWA, TAKASHI; YOSHIMURA, HIDEAKI; YAMAWAKI, SEIGO; OZAKI, NORIKAZU
To: FUJITSU LIMITED
Reel/Frame 021345/0598 →
Priority Claims (1)
JP 2007-267179 · Oct 12, 2007 · national
Continuity (1)
Related Publication 20090094825A1 · Apr 16, 2009