IP Library Patent Application 12180185
Patent Application
App. No. 12/180,185

STACKED DIE PACKAGE HAVING REDUCED HEIGHT AND METHOD OF MAKING SAME

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Quick Facts
Patent No.
US None
App. No.
12/180,185
Abstract

A stacked die package is disclosed. The stacked die package includes a wire-bond die that is electrically coupled to other components via one or more wire bonds and a flip-chip die that is coupled to the top surface of the wire-bond die via one or more solder joints. The wire-bond die is formed underneath the flip-chip die. A space defined by the height of the loops of the one or more wire-bonds overlap a space defined by the thickness of one or more solder joints.

Claims (30)

1 . A stacked die package, comprising:

a wire-bond die, wherein said wire-bond die is coupled to one or more wire bonds; and

a flip-chip die coupled to the top surface of said wire-bond die via one or more solder joints, wherein said wire-bond die is formed underneath said flip-chip die and wherein a space defined by the height of loops of said one or more wire-bonds, overlaps a space defined by the thickness of said one or more solder joints.

2 . The stacked die package of claim 1 further comprising a molding that encapsulates said wire-bond die and said flip-chip die.

3 . The stacked die package of claim 2 wherein said flip-chip die is thinned by polishing said molding that encapsulates said flip-chip die.

4 . The stacked die package of claim 3 wherein said back surface of said flip-chip die is exposed and is coincident with the top surface of said stacked die package.

5 . The stacked die package of claim 3 further comprising an external heat dissipating element that is attached to said back surface of said flip-chip die.

6 . The stacked die package of claim 1 wherein said wire-bond die comprises a redistribution layer on its top surface.

7 . The stacked die package of claim 1 further comprising staggered wire-bond pads on said wire bond die for connecting a flip chip bond to a substrate through a wire bond.

8 . A stacked die package, comprising:

a plurality of wire-bond dies coupled to one or more wire bonds; and

a flip-chip die coupled to the top surface of one of said plurality of wire-bond dies by one or more solder joints, wherein said plurality of wire-bond dies are formed underneath said flip-chip die and wherein a space defined by a vertical dimension of a wire-bond loop and a space defined by a vertical dimension of said solder joints overlap.

9 . The stacked die package of claim 8 further comprising a molding that encapsulates said wire-bond die and said flip-chip die.

10 . The stacked die package of claim 9 wherein said flip-chip die is thinned by polishing said molding that encapsulates said flip-chip die.

11 . The stacked die package of claim 10 wherein said back surface of said flip-chip die is exposed and is coincident with the top surface of said stacked die package.

12 . The stacked die package of claim 10 further comprising an external heat dissipating element that is attached to said back surface of said flip-chip die.

13 . The stacked die package of claim 8 wherein said one of said wire bond dies comprises a redistribution layer (RDL).

14 . The stacked die package of claim 8 further comprising staggered wire-bond pads on said one of said wire bond dies for connecting a flip chip bond to a substrate through a wire bond.

15 . A method for fabricating a stacked die package, comprising:

forming a substrate;

forming a wire-bond bottom die on said substrate;

forming a redistribution layer (RDL) on said wire-bond bottom die;

forming a re-layout to connect a flip-chip bond to said substrate through a wire-bond; and

forming a flip-chip die on said wire-bond bottom die, wherein said wire-bond bottom die is formed underneath said flip-chip die and wherein spaces defined by a wire-bond loop height of a wire bond associated with said wire-bond bottom die and a thickness of a solder joint associated with said flip-chip overlap.

16 . The method of claim 15 further comprising forming a molding that encapsulates said wire-bond bottom die and said flip-chip die.

17 . The method of claim 16 wherein said flip-chip die is thinned by polishing said molding that encapsulates said flip-chip die.

18 . The method of claim 17 wherein said back surface of said flip-chip die is exposed and is coincident with the top surface of said stacked die package.

19 . The method of claim 17 further comprising:

attaching an external heat dissipating element to said back surface of said flip-chip die.

20 . The method of claim 15 wherein said forming a redistribution layer further comprises forming bump-pads on said wire-bond die.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035856/0527 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2008
From: GHEE, TAN GIN; KEAT, LEOW HONG
To: SPANSION LLC
Reel/Frame 021295/0501 →