Lateral charge storage region formation for semiconductor wordline
View Patent ↗Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions formed in the semiconductor layer at both sides of the trench.
1. A semiconductor device, comprising:
a semiconductor layer including a trench extending in a first direction;
a plurality of charge storage layers formed at both side surfaces of the trench;
a first wordline buried in the trench and formed in the semiconductor layer in contact with the plurality of charge storage layers wherein the first wordline is laterally confined within vertical boundaries established by sidewalls of the trench;
a plurality of source-drain regions formed in the semiconductor layer at both sides of the trench; and
a plurality of interconnection layers extending in a second direction and parallel to one another, and configured to be selectively coupled to the plurality of source-drain regions, wherein each of the plurality of interconnection layers is coupled to only one of the plurality of source-drain regions along the first direction,
wherein the second direction is perpendicular to the first direction.
2. The semiconductor device of claim 1 , wherein the plurality of charge storage layers comprise an oxide-nitride-oxide (ONO) film.
3. The semiconductor device of claim 1 , wherein the plurality of source-drain regions are formed along the first direction.
4. The semiconductor device of claim 1 , wherein the first wordline is less than 0.2 um in width.
5. The semiconductor device of claim 1 , wherein the charge storage layers formed at the both side surfaces of the trench are connected by respective insulation films formed at a bottom of the trench across the plurality of charge storage layers.
6. The semiconductor device of claim 1 , wherein the plurality of charge storage layers are separated by an insulation portion formed in the first direction inside the trench and adapted to separate the first wordline from a second wordline, wherein the plurality of charge storage layers formed at the both side surfaces of the trench are electrically separated by the insulation portion.
7. The semiconductor device of claim 1 , wherein four of the plurality of interconnection layers are each coupled to one of four of the plurality of source-drain regions surrounding a unit of the charge storage layers.
8. The semiconductor device of claim 7 , wherein a channel is formed between two of the four of the plurality of source-drain regions along the first direction and on a same side of the trench.
9. The semiconductor device of claim 7 , wherein the unit of the charge storage layers comprises four charge storage regions.
10. The semiconductor device of claim 1 , wherein the semiconductor layer further comprises a polysilicon layer formed on a semiconductor substrate, and wherein the trench is formed on the polysilicon layer extending into the semiconductor substrate, and wherein the plurality of source-drain regions are formed in the polysilicon layer.
11. The semiconductor device of claim 1 , further comprising:
a silicide layer including a planar bottom surface that contacts top surfaces of the first word line and the plurality of charge storage layers.
12. A flash memory device, comprising:
a semiconductor layer including a polysilicon layer formed on a semiconductor substrate, wherein a trench is formed thereon extending in a first direction;
a plurality of charge storage layers formed at both side surfaces of the trench;
a first wordline buried in the trench and in contact with the plurality of charge storage layers;
a plurality of source-drain regions formed in the semiconductor layer at both sides of the trench, wherein the plurality of source-drain regions are formed in the polysilicon layer;
an inter-layer insulation film formed on the semiconductor layer covering the trench and the plurality of source drain regions; and
a plurality of elongated and continuous interconnection layers formed on the inter-layer insulation film, wherein each of the plurality of interconnection layers, extends in a second direction that is perpendicular to the first direction, and configured to be selectively coupled to only one of the plurality of source-drain regions along the first direction.
13. The flash memory device of claim 12 , wherein the plurality of charge storage layers are separated by an insulation portion formed in the first direction parallel to the sidewalls of the trench and adapted to separate the first wordline from a second wordline.
14. The flash memory device of claim 12 , wherein the plurality of interconnection layers are electrically coupled to the plurality of source-drain regions via a plurality of pad metals through the inter-layer insulation film.
15. The flash memory device of claim 12 , further comprising:
a silicide layer having a planar bottom surface that contacts top surfaces of the first word line and the plurality of charge storage layers.
16. A memory device, comprising:
a semiconductor substrate;
a plurality of trenches formed on the semiconductor substrate, extending in a first direction and parallel to one another;
an oxide-nitride-oxide (ONO) layer formed on each side surface of the plurality of trenches;
a wordline formed at least partially within each of the plurality of trenches and in contact with the ONO layers;
a first and a second plurality of source-drain regions formed in the semiconductor substrate, wherein the first and the second plurality of source-drain regions are formed respectively on opposite sides of the plurality of trenches; and
a plurality of elongated and continuous interconnection layers extending in a second direction that is perpendicular to the first direction, wherein each of the plurality of interconnection layers is configured to be electrically coupled to only the first or only the second plurality of source-drain regions along the second direction and only one of the first or the second plurality of source-drain regions along one of the trenches.
17. The memory device of claim 16 , wherein each of two adjacent interconnection layers is configured to be coupled to the first and the second plurality of source-drain regions respectively.