Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuit
An electronic design automation (EDA) tool and a method of employing unsensitized critical path information to reduce leakage power in a circuit. In one embodiment, the EDA tool includes: (1) an unsensitizable path identifier configured to receive information regarding designed devices in a circuit and information regarding identified critical paths therein, analyze a logical behavior of the circuit and identify critical and noncritical gates in unsensitizable ones of the critical paths thereof and (2) a transistor designator coupled to the unsensitizable path identifier and configured to designate relatively low threshold voltage transistors for use in the critical gates and designate relatively high threshold voltage transistors for use in the noncritical gates.
1. An electronic design automation tool embodied in program code stored in a non-transitory computer readable storage media, said program code executable by a computer, comprising:
an unsensitizable path identifier configured to receive information regarding designed devices in a circuit and information regarding identified critical paths in said circuit and identify critical and noncritical gates in unsensitizable paths of said critical paths in said circuit, wherein said noncritical gates in said unsensitizable paths of said critical paths are not gates of a sensitizable path of said critical paths of said circuit; and
a transistor designator coupled to said unsensitizable path identifier and configured to designate a first type of transistors for use in said critical gates and designate a second type of transistors for use in said noncritical gates, wherein said first type of transistors have a threshold voltage lower than said second type of transistors.
2. The electronic design automation tool as recited in claim 1 wherein said unsensitizable path identifier is configured to receive said information regarding said designed devices from a netlist.
3. The electronic design automation tool as recited in claim 1 wherein said unsensitizable path identifier is configured to receive vectors from an automatic test pattern generator and employ said vectors to identify said unsensitizable paths.
4. The electronic design automation tool as recited in claim 1 wherein said unsensitizable path identifier is configured to identify said unsensitizable paths of said critical paths using a selected one of:
a combinational analysis, and
a sequential analysis.
5. The electronic design automation tool as recited in claim 1 wherein said transistor designator is further configured to designate said second type of transistors based on transition propagation latencies of said unsensitizable paths of said critical paths.
6. The electronic design automation tool as recited in claim 1 wherein said unsensitizable path identifier is further configured to identify said critical and noncritical gates in unsensitizable paths of noncritical paths of said circuit.
7. The electronic design automation tool as recited in claim 1 wherein said circuit is an integrated circuit.
8. A method of employing unsensitized critical path information to reduce leakage power in a circuit, comprising:
identifying critical and noncritical gates in unsensitizable critical paths of said circuit, wherein said noncritical gates in said unsensitizable paths of said critical paths are not gates of a sensitizable path of said critical paths of said circuit;
designating a first type of transistors for use in said critical gates; and
designating a second type of transistors for use in said noncritical gates, wherein said first type of transistors have a threshold voltage lower than said second type of transistors and wherein said identifying step and said designating steps are executed by a computer.
9. The method as recited in claim 8 further comprising receiving information regarding designed devices in said circuit from a netlist.
10. The method as recited in claim 8 wherein said identifying comprises receiving vectors from an automatic test pattern generator.
11. The method as recited in claim 8 wherein said identifying comprises using a selected one of:
a combinational analysis, and
a sequential analysis.
12. The method as recited in claim 8 wherein said designating said second type of voltage transistors comprises designating said second type of transistors based on transition propagation latencies of said unsensitizable critical paths.
13. The method as recited in claim 8 wherein said identifying comprises identifying said critical and noncritical gates in unsensitizable noncritical paths of said circuit.
14. The method as recited in claim 8 wherein said circuit is an integrated circuit.
15. An electronic design automation tool, embodied in program code stored in a non-transitory computer readable storage media, said program code executable by a computer, comprising:
an unsensitizable path identifier configured to receive information regarding designed devices in an integrated circuit and information regarding critical and noncritical paths in said integrated circuit identified in a timing analysis of said integrated circuit and identify critical and noncritical gates in unsensitizable paths of said critical and noncritical paths of said integrated circuit; and
a transistor designator coupled to said unsensitizable path identifier and configured to designate a first type of transistors for use in said critical gates and designate a second type of transistors for use in said noncritical gates, wherein said first type of transistors have a threshold voltage lower than said second type of transistors, wherein said noncritical gates in said unsensitizable paths of said critical paths are not gates of a sensitizable path of said critical paths of said integrated circuit.
16. The electronic design automation tool as recited in claim 15 wherein said unsensitizable path identifier is configured to receive said information regarding said designed devices from a netlist.
17. The electronic design automation tool as recited in claim 15 wherein said unsensitizable path identifier is configured to receive vectors from an automatic test pattern generator and employ said vectors to identify said unsensitizable paths.
18. The electronic design automation tool as recited in claim 15 wherein said unsensitizable path identifier is configured to identify said unsensitizable paths of said critical paths using a selected one of:
a combinational analysis, and
a sequential analysis.
19. The electronic design automation tool as recited in claim 15 wherein said transistor designator is configured to designate said second type of transistors based on transition propagation latencies of said unsensitizable paths of said critical paths.
20. The electronic design automation tool as recited in claim 15 wherein said electronic design automation tool is embodied in program code stored on a non-transitory computer-readable medium.