Self-aligned cross-point memory fabrication
View Patent ↗Fabricating a cross-point memory structure using two lithography steps with a top conductor and connector or memory element and a bottom conductor orthogonal to the top connector. A first lithography step followed by a series of depositions and etching steps patterns a first channel having a bottom conductor. A second lithography step followed by a series of depositions and etching steps patterns a second channel orthogonal to the first channel and having a memory element connecting the an upper conductor and the lower conductor at their overlaid intersections.
1. A process for fabricating a cross-point memory element for a memory array comprising: applying a first lithography step to a composite multilayer structure that includes a substrate, a dielectric multilayer, and a first resist material layer whereby a pattern for a plurality of first channels is formed in the first resist material layer and in the dielectric multilayer; applying a first sequence of etching and deposition steps to form a plurality of first conductors on an area of the substrate within the first channels; applying a sequence of deposition steps to fill the plurality of first channels with a dielectric material on the first conductor and form a second resist material layer on the dielectric material thereby forming a modified composite multilayer structure; applying a second lithography step to the modified composite multilayer structure whereby a pattern for a plurality of second channels, disposed over and orthogonal to the plurality of first channels, is formed in the second resist material; applying a second sequence of etching and deposition steps to form the plurality of second channels and a plurality of connectors that make electrical contact with segments of the plurality of first conductors exposed in the second channels; and applying a third sequence of etching and deposition steps to form a plurality of second conductors that contact the connectors within the plurality of second channels wherein the second resist material layer is a composite of multiple resist layers comprising: a first layer of organic resist material disposed over the dielectric material filling the plurality of first channels; a second layer of hard mask material disposed over the first layer of organic resist material; and a third layer of resist material disposed over the second layer of hard mask material.
2. The process of claim 1 , wherein the second lithography step forms the pattern of the second channels in the third layer of resist material disposed over the second layer of hard mask material.
3. The process of claim 2 , wherein the second sequence of etching and deposition steps comprises:
a first etch step etching the pattern of the second channels through the third layer of resist material;
a second etch step etching the pattern of the second channels through the second resist material layer;
a third etch step etching away remaining third layer of resist material;
a fourth etch step etching the pattern of the second channels through the first resist material layer;
a fifth etch step etching through the dielectric material, in the second channel, through to the first conductor in areas where an etch stop layer is removed and stopping at etch stop material in areas where the etch stop layer remains, wherein portions of the first resist material layer not patterned remain on the surface of the dielectric material layer;
depositing connector material in the plurality of second channels; and
a sixth step etching away any residual connector material that resides on the first resist material layer and excess connector material in the plurality of second channels thus isolating the connector material that extends through the etch stop layer to the first conductor.
4. A process for fabricating a cross-point memory element for a memory array, comprising: applying a first lithography step to a composite multilayer structure that includes a substrate, a dielectric multilayer, and a first resist material layer whereby a pattern for a plurality of first channels is formed in the first resist material layer and in the dielectric multilayer; applying a first sequence of etching and deposition steps to form a plurality of first conductors on an area of the substrate within the first channels; applying a sequence of deposition steps to fill the plurality of first channels with a dielectric material on the first conductor, a polishing step removing any of the conducting material that extends above the dielectric material; and forming a second resist material layer on the dielectric material thereby forming a modified composite multilayer structure; applying a second lithography step to the modified composite multilayer structure whereby a pattern for a plurality of second channels, disposed over and orthogonal to the plurality of first channels, is formed in the second resist material; applying a second sequence of etching and deposition steps to form the plurality of second channels and a plurality of connectors that make electrical contact with segments of the plurality of first conductors exposed in the second channels; and, applying a third sequence of etching and deposition steps to form a plurality of second conductors that contact the connectors within the plurality of second channels wherein the third sequence of etching and deposition steps comprises: depositing a layer of conducting material to fill the plurality of second channels substantially to a surface of the first resist material layer; and an etching step removing the first resist material.
5. A process for fabricating a cross-point memory element for a memory array comprising: applying a first lithography step to a composite multilayer structure that includes a substrate, a dielectric multilayer, and a first resist material layer whereby a pattern for a plurality of first channels is formed in the first resist material layer and in the dielectric multilayer; applying a first sequence of etching and deposition steps to form a plurality of first conductors on an area of the substrate within the first channels; applying a sequence of deposition steps to fill the plurality of first channels with a dielectric material on the first conductor and form a second resist material layer on the dielectric material thereby forming a modified composite multilayer structure; applying a second lithography step to the modified composite multilayer structure whereby a pattern for a plurality of second channels, disposed over and orthogonal to the plurality of first channels, is formed in the second resist material; applying a second sequence of etching and deposition steps to form the plurality of second channels and a plurality of connectors that make electrical contact with segments of the plurality of first conductors exposed in the second channels; and applying a third sequence of etching and deposition steps to form a plurality of second conductors that contact the connectors within the plurality of second channels, wherein the composite multilayer structure comprises: a substrate; a first dielectric layer disposed on the substrate; an etch stop layer disposed on the first dielectric layer; a second dielectric layer disposed on the etch stop layer; and the first resist material layer disposed on the second dielectric layer, and wherein the modified composite multilayer structure comprises: the substrate; a plurality of first conductors formed on the substrate; a connector material over each of the plurality of first conductors; the first dielectric layer deposited in the plurality of first channels; a second layer of conducting material deposited over a surface of the first dielectric material and a surface of the connector material; and the second resist material layer, and wherein the second sequence of etching and deposition steps comprises: a first etch step etching the pattern of the second channels through the second resist material layer; and a second etch step etching the pattern of the second channels through the second layer of conductor material; and a deposition step depositing dielectric in the plurality of second channels thereby isolating the plurality of second conductors.
6. A process for fabricating a cross-point memory element for a memory array comprising: applying a first lithography step to a composite multilayer structure that includes a substrate, a dielectric multilayer, and a first resist material layer whereby a pattern for a plurality of first channels is formed in the first resist material layer and in the dielectric multilayer; applying a first sequence of etching and deposition steps to form a plurality of first conductors on an area of the substrate within the first channels; applying a sequence of deposition steps to fill the plurality of first channels with a dielectric material on the first conductors and form a second resist material layer on the dielectric material thereby forming a modified composite multilayer structure; applying a second lithography step to the modified composite multilayer structure whereby a pattern for a plurality of second channels, disposed over and orthogonal to the plurality of first channels, is formed in the second resist material; applying a second sequence of etching and deposition steps to form the plurality of second channels and a plurality of connectors that make electrical contact with segments of the plurality of first conductors exposed in the second channels; and applying a third sequence of etching and deposition steps to form a plurality of second conductors that contact the connectors within the plurality of second channels, wherein the composite multilayer structure comprises: a substrate; a first dielectric layer disposed on the substrate; an etch stop layer disposed on the first dielectric layer; a second dielectric layer disposed on the etch stop layer; and the first resist material layer disposed on the second dielectric layer, and wherein the modified composite multilayer structure comprises: the substrate; a plurality of first conductors formed on the substrate; a connector material over each of the plurality of first conductors; the first dielectric layer deposited in the plurality of first channels; a second layer of conducting material deposited over a surface of the first dielectric material and a surface of the connector material; and the second resist material layer, and wherein the third sequence of etching and deposition steps comprises: a deposition step depositing a material to fill the plurality of second channels substantially to a surface of the second layer of conductor material; and an etching step removing any residual dielectric material on the second layer of conductor material.
7. The process of claim 6 further comprising a polishing step planarizing a surface of the plurality of second conductors and the dielectric material isolating the plurality of second conductors.