Noise-tolerant data communication system
View Patent ↗This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line.
1. A data communication system comprising:
a host;
a device;
a control line connecting the host and the device so as to convey a control signal;
a clock line connecting the host and the device so as to convey a clock;
a data line connecting the host and the device so as to convey data, the data line receiving a data read-in request signal from the device and sending the data read-in request signal to the host when the control signal is at a first level, and the data read-in request signal requesting reading-in of the data by the host; and
a data line control circuit controlling the data line so that outputting of the data read-in request signal to the data line is disabled in response to first command data being inputted from the host to the device through the data line in synchronization with the clock and that the outputting of the data read-in request signal to the data line is enabled in response to second command data being inputted from the host to the device through the data line in synchronization with the clock.
2. The data communication system of claim 1 , wherein data communication between the host and the device is performed through the data line while the outputting of the data read-in request signal to the data line is disabled by the data line control circuit.
3. The data communication system of claim 1 , wherein a first address is inputted to the device through the data line when the control signal is at the first level, and the first command data is inputted to the device through the data line when the control signal is at a second level.
4. The data communication system of claim 1 , wherein a second address is inputted to the device through the data line when the control signal is at the first level, and the second command data is inputted to the device through the data line when the control signal is at a second level.
5. The data communication system of claim 3 , wherein the first address is inputted to the device through the data line when the control signal is at the first level, and the second command data is inputted to the device through the data line when the control signal is at the second level.
6. The data communication system of claim 1 , further comprising a counter to count numbers of bits of the first command data and the second command data, wherein the data line control circuit controls the data line based on the number of bits counted by the counter.
7. The data communication system of claim 2 , wherein a third address is inputted to the device through the data line when the control signal is at the first level, and the data is inputted to the device through the data line when the control signal is at a second level.
8. The data communication system of claim 2 , wherein a fourth address is inputted to the device through the data line when the control signal is at the first level, and the data is outputted from the device to the data line when the control signal is at a second level.
9. A data communication system comprising:
a host;
a device;
a control line connecting the host and the device so as to convey a control signal;
a clock line connecting the host and the device so as to convey a clock;
a data line connecting the host and the device so as to convey data, the data line receiving a data read-in request signal from the device and sending the data read-in request signal to the host when the control signal is at a first level, and the data read-in request signal requesting reading-in of the data by the host; and
a data line control circuit controlling the data line so that outputting of the data read-in request signal to the data line is disabled in response to command data being inputted from the host to the device through the data line in synchronization with the clock and that the outputting of the data read-in request signal to the data line is enabled in response to the data being outputted from the device to the data line in synchronization with the clock.
10. The data communication system of claim 9 , wherein an address is inputted to the device through the data line when the control signal is at the first level, and the data is outputted from the device to the data line when the control signal is at a second level.
11. The data communication system of claim 9 , further comprising a counter to count the number of bits of the command data, wherein the data line control circuit controls the data line based on the number of bits counted by the counter.
12. The data communication system of claim 10 , further comprising a counter to count the number of bits of the command data, wherein the data line control circuit controls the data line based on the number of bits counted by the counter.
13. A data communication system comprising:
a host;
a device;
a control line connecting the host and the device so as to convey a control signal;
a clock line connecting the host and the device so as to convey a clock;
a data line connecting the host and the device so as to convey data, the data line receiving a data read-in request signal from the device and sending the data read-in request signal to the host when the control signal is at a first level, and the data read-in request signal requesting reading-in of the data by the host; and
a data line control circuit controlling the data line so that outputting of the data read-in request signal to the data line is disabled in response to command data from the host being inputted to the device through the data line in synchronization with the clock and that the outputting of the data read-in request signal to the data line is enabled in response to the data being inputted from the host to the device through the data line in synchronization with the clock.
14. The data communication system of claim 13 , wherein the data line control circuit controls the data line so that the outputting of the data read-in request signal is enabled when the data inputted from the host to the device is of a predetermined value.
15. The data communication system of claim 13 , wherein an address is inputted to the device through the data line when the control signal is at the first level, and the data is inputted to the device through the data line when the control signal is at a second level.
16. The data communication system of claim 14 , wherein an address is inputted to the device through the data line when the control signal is at the first level, and the data is inputted to the device through the data line when the control signal is at a second level.
17. The data communication system of claim 13 , further comprising a counter to count the number of bits of the command data, wherein the data line control circuit controls the data line based on the number of bits counted by the counter.
18. The data communication system of claim 14 , further comprising a counter to count the number of bits of the command data, wherein the data line control circuit controls the data line based on the number of bits counted by the counter.
19. The data communication system of claim 15 , further comprising a counter to count the number of bits of the command data, wherein the data line control circuit controls the data line based on the number of bits counted by the counter.
20. The data communication system of claim 16 , further comprising a counter to count the number of bits of the command data, wherein the data line control circuit controls the data line based on the number of bits counted by the counter.