IP Library Granted Patent US 8,013,344
Granted Patent B2
US 8,013,344 · App. 12/186,168 · Granted Sep 6, 2011

Method of manufacturing semiconductor device and semiconductor device

Assignee: Sanyo Electric Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,013,344
App. No.
12/186,168
Granted
Sep 6, 2011
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second side closer to the lower surface, exposing a portion where the dislocation concentrated region does not exist above on the lower surface by removing the substrate on the second side along with at least a part of the dislocation concentrated region, and forming an electrode on the portion.

Claims (31)

1. A semiconductor device comprising:

a substrate including an upper surface, a lower surface and a dislocation concentrated region obliquely extending with respect to said upper surface and arranged so as to part a first side closer to said upper surface and a second side closer to said lower surface;

a semiconductor device layer formed on said upper surface; and

an electrode formed on said lower surface, wherein said semiconductor device layer includes a waveguide,

a region of said substrate under said waveguide exists within only either said first side or said second side,

a cavity facet of said waveguide is formed parallel to a (0001) plane, and

said upper surface is substantially equal to a nonpolar plane.

2. The semiconductor device according to claim 1 , wherein

said upper surface is substantially equal to a (10-10) plane, (−2110) plane or a plane equivalent to these planes.

3. The semiconductor device according to claim 1 , wherein

said dislocation concentrated region is so arranged as to extend from said first side to said second side.

4. The semiconductor device according to claim 1 , wherein

said waveguide is so formed as to be located above a first region except a first area where said dislocation concentrated region is present in said upper surface.

5. The semiconductor device according to claim 1 , wherein

said waveguide is so formed as to be located above a second region except a second area where said dislocation concentrated region is present in said lower surface.

6. The semiconductor device according to claim 1 , wherein said waveguide extends along a [0001] direction.

7. The semiconductor device according to claim 1 , wherein said substrate and said semiconductor device layer are made of a nitride-based semiconductor.

8. The semiconductor device according to claim 1 , wherein said semiconductor device layer is a semiconductor light-emitting device layer including an emission layer.

9. A semiconductor device comprising:

a substrate including an upper surface, a lower surface and a dislocation concentrated region obliquely extending with respect to said upper surface and arranged so as to part a first side closer to said upper surface and a second side closer to said lower surface;

a semiconductor device layer formed on said upper surface; and

an electrode formed on said lower surface, wherein said semiconductor device layer includes a waveguide,

a region of said substrate under said waveguide exists within only either said first side or said second side,

a cavity facet of said waveguide is formed parallel to a (0001) plane, and said dislocation concentrated region is formed parallel to a (11-20) plane.

10. A semiconductor device comprising:

a substrate including an upper surface, a lower surface and a dislocation concentrated region obliquely extending with respect to said upper surface and arranged so as to part a first side closer to said upper surface and a second side closer to said lower surface;

a semiconductor device layer formed on said upper surface; and

an electrode formed on said lower surface, wherein said semiconductor device layer includes a waveguide,

a region of said substrate under said waveguide exists within only either said first side or said second side, and

a cavity facet of said waveguide is formed parallel to a (0001) plane, the semiconductor device further comprising a ridge formed on said upper surface, wherein

said waveguide is formed on a lower domain of said ridge.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2017
From: SANYO ELECTRIC CO., LTD.
To: EPISTAR CORPORATION
Reel/Frame 041652/0122 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2016
From: FUTURE LIGHT LIMITED LIABILITY COMPANY
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 040523/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2012
From: SANYO ELECTRIC CO., LTD.
To: FUTURE LIGHT, LLC
Reel/Frame 027957/0258 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2008
From: MIYAKE, YASUTO; HIROYAMA, RYOJI; HATA, MASAYUKI
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 021341/0919 →
Priority Claims (1)
JP 2007-203748 · Aug 6, 2007 · national
Continuity (1)
Related Publication 20090039473A1 · Feb 12, 2009