Semiconductor device and manufacturing method of the same
View Patent ↗An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.
1. A semiconductor device comprising:
a semiconductor substrate of a first general conductivity type configured to operate as a back gate region;
a channel region of a second general conductivity type disposed on the semiconductor substrate;
a source region and a drain region of the second general conductivity type formed in a surface portion of the channel region;
a gate region of the first general conductivity type formed between the source region and the drain region in the surface portion of the channel region; and
an impurity region of the second general conductivity type disposed between the semiconductor substrate and the channel region so as to be located below the gate electrode, an impurity concentration of the impurity region being higher than an impurity concentration of the channel region,
wherein the channel region covers the entire bottom of the source region and the drain region.
2. The semiconductor device of claim 1 , wherein the impurity region, in a plan view of the semiconductor device, covers an area between the source region and the drain region.
3. The semiconductor device of claim 1 , further comprising an isolation region formed in the channel region to surround the source region and the drain region in a plan view of the semiconductor device, wherein the impurity region, in the plan view, covers the entire area between the source region and the drain region and is not in contact with the isolation region.
4. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate of a first general conductivity type;
forming an impurity region of a second general conductivity type in a surface portion of the semiconductor substrate;
forming a semiconductor layer of the second general conductivity type on the impurity region;
forming an isolation region in the semiconductor layer so as to penetrate the semiconductor layer to reach the semiconductor substrate, the isolation region defining a channel region made of the semiconductor layer disposed on the impurity region;
forming a gate region of the first general conductivity type in a surface portion of the channel region;
forming a source region and a drain region of the second general conductivity type in the surface portion of the channel region so that the channel region covers the entire bottom of the source region and the drain region; and
configuring the semiconductor substrate to operate as a back gate.
5. The method of claim 4 , wherein the impurity region is formed to cover, in a plan view of the semiconductor substrate, a portion of channel region between the source region and the drain region.
6. The method of claim 4 , wherein the impurity region is formed to cover, in a plan view of the semiconductor substrate, the entire portion of channel region between the source region and the drain region and is not in contact with the isolation region.