ESD power clamp with stable power start up function
An integrated circuit including a first power rail, a second power rail, a power clamp connected between the first and second power rails; and a trigger circuit connected to the power clamp and the first second power rails. The trigger circuit includes an RC element formed on the basis of field effect transistors, first inverter stage connected to the RC element, a second inverter stage, and a third inverter stage. The first, second and third inverter stages are connected in series to a control input of the power clamp. The trigger circuit also included a feed back connection from an output of the second inverter stage to the first inverter stage.
1. An integrated circuit comprising:
a first power rail;
a second power rail;
a power clamp connected between said first and second power rail; and
a trigger circuit connected to said power clamp and said first and second power rails, said trigger circuit comprising:
an RC element formed on the basis of field effect transistors,
a first inverter stage connected to said RC element, a second inverter stage and a third inverter stage, said first, second and third inverter stages connected in series to a control input of said power clamp, said trigger circuit further comprising a positive feedback connection from an output of said second inverter stage to said first inverter stage, wherein the positive feedback connection causes a resistance in a current path internal to the first inverter stage between the first power rail and an output of said first inverter stage to vary in response to variations in a voltage at the output of said second inverter stage.
2. The integrated circuit of claim 1 , wherein said positive feedback connection comprises a feedback p-channel transistor that has a resistance that varies in response to variations in the voltage at the output of said second inverter stage.
3. The integrated circuit of claim 2 , wherein an output node of said first inverter stage is connected to a drain terminal of an n-channel transistor of said first inverter stage and said feedback p-channel transistor is connected with its channel between said output node and a drain terminal of a p-channel transistor of said first inverter stage.
4. The integrated circuit of claim 3 , wherein a gate terminal of said feedback p-channel transistor is connected to an output node of said second inverter stage.
5. The integrated circuit of claim 2 , wherein the resistance of the feedback p-channel transistor decreases in response to the voltage at the output of said second inverter stage decreasing so that a rise time of an output node of said first inverter stage is less than a rise time of an output node of said second inverter stage for a voltage across said first and second power rails having a rise time of approximately 100 nanoseconds or less.
6. The integrated circuit of claim 2 , wherein the resistance of the feedback p-channel transistor increases in response to the voltage at the output of said second inverter stage increasing so that a rise time of the output node of said first inverter stage is greater than a rise time of the output node of said second inverter stage for a voltage across said first and second power rails having a rise time of approximately 200 nanoseconds or more.
7. The integrated circuit of claim 1 , further comprising a first p-channel transistor connected with its source/drain path between said first power rail and said second inverter stage, wherein a gate terminal of said first p-channel transistor is connected to said control input of said power clamp.
8. The integrated circuit of claim 7 , further comprising a second p-channel transistor connected with its source/drain path between an output node of said second inverter stage and said first power rail, wherein a gate terminal of said second p-channel transistor is connected to said control input of said power clamp.
9. The integrated circuit of claim 1 , wherein said power clamp comprises an n-channel transistor.
10. The integrated circuit of claim 1 , further comprising a plurality of input/output pads and an ESD circuit connected to said plurality of input/output pads and configured to discharge positive excess charge to said first power rail and to discharge negative excess charge to said second power rail.
11. An integrated circuit comprising:
a power clamp configured to be connected between a first power rail terminal and a second power rail terminal;
an RC element configured to be connected between said first and second power rail terminals,
a first inverter stage connected to said RC element, a second inverter stage, and a third inverter stage, wherein said first, second and third inverter stages are connected in series to a control input of said power clamp; and
a positive feedback connection from an output of said second inverter stage to said first inverter stage, wherein the positive feedback connection causes a resistance in a current path internal to the first inverter stage between the first power rail terminal and an output of said first inverter stage to vary in response to variations in a voltage at the output of said second inverter stage.
12. The integrated circuit of claim 11 , wherein said feedback connection comprises a feedback p-channel transistor that has a resistance that varies in response to variations in the voltage at the output of said second inverter stage.
13. The integrated circuit of claim 12 , wherein the resistance of the feedback p-channel transistor decreases in response to the voltage at the output of said second inverter stage decreasing so that a rise time of an output node of said first inverter stage is less than a rise time of an output node of said second inverter stage for a voltage across said first and second power rail terminals having a rise time of approximately 100 nanoseconds or less.
14. The integrated circuit of claim 12 , wherein the resistance of the feedback p-channel transistor increases in response to the voltage at the output of said second inverter stage increasing so that a rise time of the output node of said first inverter stage is greater than a rise time of the output node of said second inverter stage for a voltage across said first and second power rail terminals having a rise time of approximately 200 nanoseconds or more.
15. The integrated circuit of claim 11 , further comprising a first p-channel transistor configured to be connected with its source/drain path between said first power rail and said second inverter stage, wherein a gate terminal of said first p-channel transistor is connected to said control input of said power clamp.
16. The integrated circuit of claim 15 , further comprising a second p-channel transistor configured to be connected with its source/drain path between an output node of said second inverter stage and said first power rail terminal, wherein a gate terminal of said second p-channel transistor is connected to said control input of said power clamp.
17. The integrated circuit of claim 11 , comprising a plurality of input/output pads and an ESD circuit connected to said plurality of input/output pads and configured to discharge positive excess charge to said first power rail terminal and to discharge negative excess charge to said second power rail terminal.
18. The integrated circuit of claim 11 , comprising the first and second power rails coupled to the first and second power rail terminals, respectively.
19. An integrated circuit comprising:
a power clamp configured to be connected between first and second power rail terminals;
an RC element configured to be connected between said first and second power rail terminals,
a first inverter stage connected to said RC element, a second inverter stage, and a third inverter stage, wherein said first, second and third inverter stages are connected in series to a control input of said power clamp; and
a positive feedback connection from an output of said second inverter stage to an internal circuit path in said first inverter stage, wherein the positive feedback connection causes a rise time of the output node of said first inverter stage to vary in response to variations in a voltage at the output of said second inverter stage.
20. The integrated circuit of claim 19 , wherein said positive feedback connection comprises a feedback p-channel transistor in said first inverter stage, the feedback p-channel transistor having a resistance that varies in response to variations in the voltage at the output of said second inverter stage.
21. The integrated circuit of claim 20 , wherein the resistance of the feedback p-channel transistor decreases in response to the voltage at the output of said second inverter stage decreasing so that the rise time of an output node of said first inverter stage is less than a rise time of an output node of said second inverter stage for a voltage across said first and second power rail terminals having a rise time of approximately 100 nanoseconds or less.
22. The integrated circuit of claim 20 , wherein the resistance of the feedback p-channel transistor increases in response to the voltage at the output of said second inverter stage increasing so that the rise time of the output node of said first inverter stage is greater than a rise time of the output node of said second inverter stage for a voltage across said first and second power rails having a rise time of approximately 200 nanoseconds or more.