ERASEABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE
A nonvolatile storage cell, integrated circuit (IC) including the cells and method of manufacturing the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride layer) in the layered spacer.
1 . A method of forming nonvolatile storage cells in an integrated circuit, said method comprising the steps of:
a) forming gates in cell locations;
b) forming a first isolation layer on said cell locations;
c) forming charge storage sidewall spacers at said gates;
d) forming a second isolation layer on said cell locations; and
e) forming an outer sidewall spacer adjacent to said gates, each of said charge storage sidewall spacers being between one of said gates and one said outer sidewall spacer.
2 . A method of forming nonvolatile storage cells as in claim 1 , wherein said first isolation layer and said second isolation layer are oxide layers and said charge storage sidewall spacers and outer sidewall spacers are nitride sidewall spacers.
3 . A method of forming nonvolatile storage cells as in claim 2 , further comprising forming source/drain diffusions on either side of each of said gates, said source/drain diffusions at said outer sidewall spacers underlapping said gates.
4 . A method of forming nonvolatile storage cells as in claim 3 , wherein said source/drain diffusions at said outer sidewall spacers underlap said gates at least to said charge storage layer.
5 . A method of forming nonvolatile storage cells as in claim 4 , wherein said charge storage sidewall spacers and outer sidewall spacers are formed at both end of said gates in ones of said nonvolatile storage cells, said ones of said nonvolatile storage cells storing two bits each.