Granted Patent B1

US 7,971,169 · App. 12/190,784 · Granted Jun 28, 2011

Abstract

Claims (44)

1. A system for reducing the generation of inconsequential violations resulting from timing analyses, comprising:

an unsensitizable path identifier configured to identify at least some unsensitizable paths in a circuit before other steps;

a parasitic parameter extraction tool configured to extract parasitic parameters in said circuit in a second step;

a timing violation identifier configured to identify at least some timing violations in said circuit based on a timing analysis in a third step, wherein said timing analysis uses said extracted parasitic parameters; and

a repair list generator coupled to said timing violation identifier and said unsensitizable path identifier and configured to generate a repair list based on both said at least some timing violations and said at least some unsensitizable paths.

2. The system as recited in claim 1 wherein said timing analysis includes at least one selected from the group consisting of:

a static timing analysis, and

a statistical timing analysis.

3. The system as recited in claim 1 wherein said unsensitizable path identifier is configured to identify said unsensitizable paths based on sensitizable paths identified in said circuit.

4. The system as recited in claim 1 wherein said repair list contains a reduced number of timing violations attributable to unsensitizable paths in said circuit.

5. The system as recited in claim 1 wherein a netlist describing said circuit is employed as a common source of information for both said timing analysis and an identification of sensitizable paths in said circuit.

6. The system as recited in claim 1 wherein said timing analysis is based on extracted parasitic parameters and said at least some unsensitizable paths are based on output from a logic simulator tool.

7. The system as recited in claim 1 wherein said circuit is an integrated circuit.

8. The system as recited in claim 1 wherein said timing violation identifier, said an unsensitizable path identifier and said repair list generator are embodied in program code stored on a non-transitory computer-readable medium.

9. A method of reducing the generation of inconsequential violations resulting from timing analyses, comprising:

identifying at least some unsensitizable paths in a circuit before other steps;

extracting parasitic parameters from said circuit in a second step;

identifying at least some timing violations in said circuit based on a timing analysis in a third step, wherein said timing analysis uses said extracted parasitic parameters; and

generating a repair list based on both said at least some timing violations and said at least some unsensitizable paths, wherein said steps are performed by a processor.

10. The method as recited in claim 9 wherein said timing analysis is carried out by carrying out at least one selected from the group consisting of:

a static timing analysis, and

a statistical timing analysis.

11. The method as recited in claim 9 wherein said identifying said at least some unsensitizable paths comprises identifying said unsensitizable paths based on sensitizable paths identified in said circuit.

12. The method as recited in claim 9 wherein said repair list contains a reduced number of timing violations attributable to unsensitizable paths in said circuit.

13. The method as recited in claim 9 further comprising employing a netlist describing said circuit as a common source of information for both said timing analysis and an identification of sensitizable paths in said circuit.

14. The method as recited in claim 9 further comprising:

basing said timing analysis on extracted parasitic parameters; and

basing said at least some unsensitizable paths on output from a logic simulator tool.

15. The method as recited in claim 9 wherein said circuit is an integrated circuit.

16. An electronic design automation tool, comprising:

a parasitic parameter extraction tool configured to extract parasitic parameters associated with a circuit;

a timing analysis tool configured to perform a timing analysis based on said parasitic parameters;

a logic simulator tool configured to simulate logic in said circuit;

and

a system for reducing the generation of inconsequential violations resulting from timing analyses, including:

an unsensitizable path identifier configured to identify at least some unsensitizable paths in a circuit based on said sensitizable paths before other steps,

a timing violation identifier configured to identify at least some timing violations in said circuit based on said timing analysis in a next step, wherein said timing analysis uses said extracted parasitic parameters, and

a repair list generator coupled to said timing violation identifier and said unsensitizable path identifier and configured to generate a repair list based on both said at least some timing violations and said at least some unsensitizable paths.

17. The tool as recited in claim 16 wherein said timing analysis tool is selected from the group consisting of:

a static timing analysis tool, and

a statistical timing analysis tool.

18. The tool as recited in claim 16 wherein said repair list contains a reduced number of timing violations attributable to unsensitizable paths in said circuit.

19. The tool as recited in claim 16 wherein a netlist describing said circuit is employed as a common source of information for both said parasitic parameter extraction tool and said logic simulator tool.

20. The tool as recited in claim 16 wherein said circuit is an integrated circuit.

Assignments (9)