Semiconductor chip, method of fabricating the same and stacked package having the same
View Patent ↗A semiconductor chip, a method of fabricating the same and a stacked package having the same are disclosed. The semiconductor chip includes a wafer, a semiconductor device disposed on the wafer, an insulating layer covering the semiconductor device and disposed on the wafer, a deep via formed to penetrate the wafer and the insulating layer, and a heat dissipation member spaced at a predetermined interval from the deep via and penetrating at least a portion of the insulating layer for dissipating heat generated by the deep via.
1. A semiconductor chip comprising:
a wafer;
a semiconductor device disposed on the wafer;
a first insulating layer formed on the wafer including the semiconductor device;
a second insulating layer on the first insulating layer;
a deep via formed penetrating through the wafer, the first insulating layer, and the second insulating layer; and
a heat dissipation member spaced a predetermined distance from the deep via and penetrating at least a portion of the first and second insulating layers for dissipating heat generated by the deep via,
wherein the heat dissipation member includes:
a plurality of first vias penetrating through the first insulating layer;
a first heat transferring member disposed on the first insulating layer and connected to the first vias;
a plurality of second vias penetrating through the second insulating layer and being connected to the first heat transferring member; and
a second heat transferring member disposed on the second insulating layer and connected to the second vias.
2. The semiconductor chip of claim 1 , further comprising a buffer layer formed on and covering the deep via.
3. The semiconductor chip of claim 1 , further comprising a redistribution layer formed on a distal end of the deep via and electrically connected to the deep via and the semiconductor device.
4. The semiconductor chip of claim 3 , wherein the redistribution layer comprises a first redistribution layer formed on the deep via and a second redistribution layer formed on the first redistribution layer.
5. The semiconductor chip of claim 1 , wherein the predetermined distance is in a range between 2 μm to 5 μm.