U-shaped SONOS memory having an elevated source and drain
View Patent ↗A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial semiconductor layers.
1. A semiconductor device comprising:
a plurality of epitaxial semiconductor layers formed on a semiconductor substrate;
a plurality of bit lines formed on upper portions of the plurality of epitaxial semiconductor layers;
a charge storage layer formed on the semiconductor substrate between the plurality epitaxial semiconductor layers; and
a mask layer on a region corresponding to the area between the plurality of epitaxial semiconductor layers,
wherein the plurality of epitaxial semiconductor layers are formed using the mask layer as a mask,
further wherein the plurality of epitaxial semiconductor layers are polished to be in the same plane with the mask layer.
2. The semiconductor device according to claim 1 , wherein:
a groove is formed in the semiconductor substrate between the plurality of epitaxial semiconductor layers; and
the charge storage layer is formed along an inner surface of the groove.
3. The semiconductor device according to claim 1 , wherein each of the plurality of epitaxial semiconductor layers is formed as a bit line.
4. The semiconductor device according to claim 1 , wherein the charge storage layer is also formed on each side of the plurality of epitaxial semiconductor layers.
5. A method for manufacturing a semiconductor device comprising:
forming a charge storage layer on a region of a semiconductor substrate corresponding to an area between a plurality of epitaxial semiconductor layers;
forming the plurality of epitaxial semiconductor layers on the semiconductor substrate;
forming a bit line on each upper portion of the plurality of epitaxial semiconductor layers;
forming a mask layer on a region corresponding to the area between the plurality of epitaxial semiconductor layers, wherein the plurality of epitaxial semiconductor layers are formed using the mask layer as a mask; and
polishing the plurality of epitaxial semiconductor layers to be in the same plane with the mask layer.
6. The method for manufacturing a semiconductor device according to claim 5 , further comprising forming a groove in the region of the semiconductor substrate corresponding to the area between the plurality of epitaxial semiconductor layers, wherein the charge storage layer is formed along an inner surface of the groove.
7. The method for manufacturing a semiconductor device according to claim 5 , wherein the plurality of epitaxial semiconductor layers are formed using the charge storage layer as a mask.
8. The method for manufacturing a semiconductor device according to claim 5 , wherein the plurality of epitaxial semiconductor layers are formed to have each upper surface lower than an upper surface of the mask layer.