Semiconductor device having an increased area of one of the opposing electrode parts for preventing generation of unconnected positions the electrodes on the bonded wafers

1. A semiconductor device comprising:

a first wafer ( 1 WA) and a second wafer ( 1 WB) that are bonded together at a bonding surface ( 30 a );

a plurality of first electrical signal connection parts ( 9 ), extending from within the first wafer ( 1 WA), across the bonding surface ( 30 a ) between the first wafer ( 1 WA) and the second wafer ( 1 WB), and into the second wafer ( 1 WB);

a plurality of second electrical signal connection parts ( 26 ), provided on a bonding surface ( 30 b ) within the second wafer ( 1 WB), and forming a plurality of inter-wafer connection parts ( 30 c ) at a central portion thereof that electrically connect to each of the first electrical signal connection parts ( 9 );

wherein:

each of the first electrical signal connection parts ( 9 ) is enclosed by a penetrating isolation part ( 5 ) which electrically insulate the inter-wafer connection parts ( 30 c ) from each other, each of the penetrating isolation parts ( 5 ) having walls arranged in a rectangular shape and which extend from the bonding surface ( 30 b ) within the second wafer ( 1 WB), across the bonding surface ( 30 a ) between the first wafer ( 1 WA) and the second wafer ( 1 WB), and into the first wafer ( 1 WA); and

a junction face shape (A 3 , A 4 ) of each of the second electrical signal connection parts ( 26 ) is larger than a shape (A 2 ) of a positioning margin face that is formed by an outer shape (A 2 ) when a minimum junction shape (A 1 ), which has an area that is half of a junction area of the first electrical signal connection part ( 9 ), is enclosed by a same width dimension (M 1 ) as a positioning margin dimension between (M 1 ) the first wafer ( 1 WA) and the second wafer ( 1 WB).

2. The semiconductor device according to claim 1 , wherein:

when a difference between the distance from a center (C) of the first wafer ( 1 WA) and the first electrical signal connection parts ( 9 ) arranged in an outermost portion of the first wafer ( 1 WA), and the distance from the center (C) of a pre-processed substrate ( 1 SA) that becomes the first wafer ( 1 WA) and pre-processed parts that become the first electrical signal connection parts ( 9 ) arranged in the outermost portion of the pre-processed substrate ( 1 SA), is deemed to be a post-processing positioning margin dimension (M 2 ); and

the junction face shape of each of the second electrical signal connection parts ( 26 ) is the same as the shape (A 3 ) of a post-processing positioning margin face formed when the periphery of the shape (A 2 ) of the positioning margin face is enclosed by the same width as that of the post-processing positioning margin dimension (M 2 ).

3. The semiconductor device according to claim 2 , wherein:

the junction face shape of the second electrical signal connection parts ( 26 ) is the same as a corrected outer shape (A 4 ) when the periphery (P) of the shape (A 3 ) of the post-processing positioning margin face is enclosed by a predetermined correction dimension (M 3 ) of no more than 2.5 μm.

4. The semiconductor device according to claim 1 , wherein the first wafer ( 1 WA) or the second wafer ( 1 WB) is a thinned wafer which is subjected to a thickness reduction process.

5. The semiconductor device according to claim 1 , wherein:

the first electrical signal connection parts ( 9 ) are penetrating wiring parts ( 9 ) which electrically connects one face of the first wafer ( 1 WA) with another face thereof; and

the second electrical signal connection parts ( 26 ) are bumps ( 26 ).