Implementation of recycling unused ECC parity bits during flash memory programming
Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed.
1. A method for recycling error correction code (ECC) during flash memory programming, comprising:
calculating a first ECC syndrome from a first user data;
storing the syndrome with the first user data into a memory as stored data;
calculating a second ECC syndrome from both the stored data and a second user data;
comparing the second syndrome with the first syndrome;
determining if the first syndrome is able to be recycled based upon the comparison; and
selectively re-encoding the first ECC syndrome if determined that the first syndrome is able to be recycled.
2. The method of claim 1 , further comprising indicating that the first ECC syndrome has failed and not able to be recycled if a ‘1’ bit would be programmed over by a ‘0’ bit.
3. The method of claim 2 , wherein indicating that the first ECC syndrome has failed comprises programming an indicator bit associated with the first ECC.
4. The method of claim 1 , further comprises inhibiting use of the first ECC syndrome if determined it is not able to be recycled by programming an indicator bit.
5. The method of claim 4 , wherein the indicator bit inhibits use of the first ECC syndrome of the first user data and wherein the first syndrome is the syndrome stored most recently prior to calculating the second ECC syndrome.
6. The method of claim 1 , wherein selectively re-encoding the first ECC syndrome comprises programming a ‘0’ bit and not a ‘1’ bit.
7. The method of claim 1 , wherein selectively re-encoding the first ECC syndrome comprises programming a ‘0’ bit to a ‘1’ bit when it is able to be recycled.
8. The method of claim 1 , further comprises not re-encoding the first ECC syndrome with the second ECC syndrome when a programmed data would be programmed over by an erase data.
9. The method of claim 1 , wherein storing the user data in the memory cells further comprises storing verified ECC parity code data and wherein the memory is a volatile memory or SRAM memory.
10. The method of claim 1 , wherein the first ECC syndrome is a core ECC parity that corresponds to the first user data and wherein the first syndrome is the most recent syndrome stored prior to calculating the second ECC syndrome.
11. A method of recycling unused error correction code (ECC) bits during flash programming, comprising:
programming a first data into first ECC parity bits to form a stored data block; and
selectively re-encoding the first ECC parity bits based on the most recently stored data block and a second data.
12. The method of claim 11 , wherein selectively re-encoding comprises programming an erased data with a programmed data and abandoning re-encoding if a programmed data will be programmed with an erased data.
13. The method of claim 12 , wherein abandoning re-encoding comprises programming an indicator bit associated with the ECC parity bits to inhibit the use of the ECC parity bits for recycling.
14. The method of claim 12 , wherein selectively re-encoding ECC parity bits further comprises:
generating second ECC parity bits based on the stored data block and second data; and
verifying the second ECC parity bits are able to recycle the first ECC parity bits by comparing the second ECC parity bits with the stored data block.
15. The method of claim 14 , wherein verifying comprises programming an indicator bit if the first ECC parity bits cannot be selectively re-encoded.
16. The method of claim 14 , wherein the second ECC is an expected ECC parity data based on the second data and the stored data block, and is an output of an ECC encoder.
17. The method of claim 16 , wherein the indicator bit inhibits the use of an associated ECC parity.
18. The method as set forth in claim 16 , further comprises selectively re-encoding a ‘1’ over a ‘0’ second data into the first ECC parity comprises programming a ‘1’ over a ‘0’.
19. The method of claim 11 , wherein selectively re-encoding comprises programming a ‘1’ bit over a ‘0’ bit and detecting if a ‘0’ bit would be programmed over a ‘1’ bit.
20. A communication device, comprising:
a flash memory CPU;
a flash memory operatively coupled to the flash memory CPU and configured to transfer data to and from the flash memory CPU;
an input component for entering the data;
a display component for displaying information;
a plurality of switches;
flash memory; and
a method of recycling unused error correction code (ECC) during flash programming, comprising:
calculating a first ECC syndrome from a first user data;
storing the syndrome with the first user data into a memory as stored data;
calculating a second ECC syndrome from both the stored data and a second user data;
comparing the second syndrome with the first syndrome;
determining if the first syndrome is able to be recycled based upon the comparison; and
selectively re-encoding the first ECC syndrome if determined that the first syndrome is able to be recycled.