Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an impurity region when impurities in the impurity region are thermally diffused in a semiconductor substrate. A second photoresist is formed on an insulation film. The second photoresist is formed to have second openings K 2 on both sides of a P-type impurity region so that the second openings K 2 partially overlap the P-type impurity region. The insulation film is etched off together with an underlying surface of the semiconductor substrate using the second photoresist as a mask so as to remove the P-type impurity region partially. Then, phosphorus ions (P+) are implanted into the surface of the semiconductor substrate in the etched-off regions using the second photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After removing the second photoresist, the impurities in the P-type impurity region and the impurities in the N-type impurity region are thermally diffused.
1. A semiconductor device comprising:
a semiconductor substrate of a first general conductivity type;
a semiconductor layer of a second general conductivity type disposed on the semiconductor substrate; and
an isolation region of the first general conductivity type formed in the semiconductor layer so as to surround and electrically isolate a portion of the semiconductor layer,
wherein a width of an upper end of the isolation region is smaller than a width of an lower end of the isolation region.
2. The semiconductor device of claim 1 , further comprising a depressed portion formed in the semiconductor layer so as to be adjacent the isolation region.
3. The semiconductor device of claim 1 , further comprising a semiconductor element disposed in the semiconductor layer.
4. The semiconductor device of claim 2 , further comprising a semiconductor element disposed in the semiconductor layer.