Method of processing semiconductor wafer
View Patent ↗Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.
1. A method of processing a semiconductor wafer, comprising:
providing a semiconductor wafer of a first general conductivity type;
growing a first epitaxial semiconductor layer of the first general conductivity type only from the semiconductor wafer;
etching the first epitaxial semiconductor layer to form a plurality of trenches;
growing a second epitaxial semiconductor layer of a second general conductivity type from the etched first epitaxial semiconductor layer so as to leave a void in each trench;
etching the second epitaxial semiconductor layer so as to expose a top surface of the first epitaxial semiconductor layer;
growing a third epitaxial semiconductor layer of the first general conductivity type from the exposed top surface of the first epitaxial semiconductor layer and the etched second epitaxial semiconductor layer in the trenches so that the voids are filled at least partially with the third epitaxial semiconductor layer; and
etching the third epitaxial semiconductor layer so as to expose the top surface of the first epitaxial semiconductor layer and a top surface of the second epitaxial semiconductor layer,
wherein the first epitaxial semiconductor layer has substantially the same impurity concentration as the third epitaxial semiconductor layer.
2. The method of claim 1 , wherein a portion of the first epitaxial semiconductor layer damaged during the formation of the trenches is removed by thermal oxidation.
3. A method of processing a semiconductor wafer, comprising:
providing a semiconductor wafer of a first general conductivity type;
growing a first epitaxial semiconductor layer of the first general conductivity type from the semiconductor wafer;
etching the first epitaxial semiconductor layer to form a plurality of trenches;
growing a second epitaxial semiconductor layer of a second general conductivity type from the etched first epitaxial semiconductor layer so as to leave a void in each trench;
etching the second epitaxial semiconductor layer so as to expose a top surface of the first epitaxial semiconductor layer;
growing a third epitaxial semiconductor layer of the first general conductivity type from the exposed top surface of the first epitaxial semiconductor layer and the etched second epitaxial semiconductor layer in the trenches so that the voids are not filled fully with the third epitaxial semiconductor layer;
etching the third epitaxial semiconductor layer so as to expose the top surface of the first epitaxial semiconductor layer and a top surface of the second epitaxial semiconductor layer;
growing a fourth epitaxial semiconductor layer of the second general conductivity type from the exposed top surfaces of the first and second epitaxial semiconductor layers and the etched third epitaxial semiconductor layer in the voids; and
etching the fourth epitaxial semiconductor layer so as to expose the top surfaces of the first and second epitaxial semiconductor layers and a top surface of the third epitaxial semiconductor layer.
4. The method of claim 3 , wherein impurity concentration profiles of the first to fourth epitaxial semiconductor layers are uniform in a direction vertical to the semiconductor wafer surface.
5. The method of claim 1 , wherein the first epitaxial semiconductor layer is grown from the semiconductor wafer so as to be substantially flat.