Semiconductor trench structure having a sealing plug and method
View Patent ↗In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.
1. A method for forming a semiconductor device comprising the steps of:
providing a region of semiconductor material having a major surface;
forming a trench extending from the major surface;
forming a first dielectric layer overlying surfaces of the trench;
forming a second dielectric layer overlying the first dielectric layer, wherein the first and second dielectric layers comprise different materials;
removing portions of the first dielectric layer along upper portions of the trench to provide exposed sidewall portions while using the second dielectric layer as a masking layer;
removing the second dielectric layer; and
forming a semiconductor plug extending from the exposed sidewall portions.
2. The method of claim 1 , wherein the step of forming the semiconductor plug comprises the step of selectively growing an epitaxial single crystal semiconductor plug extending from the exposed sidewall portions.
3. The method of claim 1 , wherein the step of forming semiconductor plug comprises the step of sealing the trench with the semiconductor plug to form a sealed core, and wherein the sealed core is under vacuum.
4. The method of claim 1 further comprising the steps of forming at least two single crystal semiconductor layers having opposite conductivity type overlying surfaces of the trench before the step of forming the first dielectric layer.
5. The method of claim 1 , wherein the step of forming the first dielectric layer comprises forming a silicon oxide, and wherein the step of forming the second dielectric layer comprises forming a silicon nitride layer.
6. The method of claim 1 , wherein the step of removing portions of the first dielectric layer includes isotropically etching portions of the first dielectric layer.
7. The method of claim 1 , wherein the step of forming the semiconductor plug includes forming a semiconductor plug having a conductivity type opposite to that of the region of semiconductor material.