Semiconductor device and a method of manufacturing the same
View Patent ↗In the present invention, an npn junction is formed by circularly forming a p− type impurity region and n+ type impurity regions on a same single-crystalline substrate as a MOS transistor. Multiple npn junctions are formed apart from each other in concentric circular patterns. With this configuration, steep breakdown characteristics can be obtained, which results in good constant-voltage diode characteristics. Being formed in a manufacturing process of a MOS transistor, the present protection diode contributes to process streamlining and cost reduction. By selecting the number of npn junctions according to breakdown voltage, control of the breakdown voltage can be facilitated.
1. A semiconductor device comprising:
a vertical metal oxide semiconductor transistor formed in a single-crystalline semiconductor substrate of a first general conductivity type and comprising a gate electrode and a source electrode; and
a protection element comprising a first impurity region of a second general conductivity type formed in the single-crystalline semiconductor substrate, a second impurity region of the first general conductivity type formed in the first impurity region and a third impurity region of the first general conductivity type formed in the first impurity region and separated away from the second impurity region, the first, second and third impurity regions being concentric,
wherein the second impurity region is connected to the gate of the transistor, and the third impurity region is disposed outside the second impurity region and connected to the source of the transistor.
2. The semiconductor device of claim 1 , wherein the first, second and third impurity regions are circular.
3. The semiconductor device of claim 2 , wherein the first circular impurity region comprises a plurality of circular and concentric sub-regions of the second general conductivity type separated from each other, the second circular impurity region is disposed in the most inner sub-region, the third circular impurity region is disposed in the most outer sub-region, and a portion of the protection element comprising the most inner sub-region and a portion of the protection element comprising the most outer sub-region are connected in series.
4. The semiconductor device according to claim 2 , wherein the first circular impurity region has an impurity concentration of a channel layer of the transistor.
5. The semiconductor device of claim 2 , further comprising an insulating film formed on the single-crystalline semiconductor substrate so as to cover a region of the substrate in which the first, second and third circular impurity regions are formed, and a conductor layer formed on the insulating film and connected to the gate electrode.
6. A method of manufacturing a semiconductor device comprising a vertical metal oxide semiconductor transistor and a protection element for the transistor, comprising:
providing a single-crystalline semiconductor substrate of a first general conductivity type;
forming a impurity region of a second general conductivity type in the single-crystalline semiconductor substrate;
forming two impurity regions of the first general conductivity type in the impurity region of the second general conductivity type so as to be concentric with the impurity region of the second general conductivity type;
connecting one of the two impurity regions of the first general conductivity type to a gate of the transistor; and
connecting another of the two impurity regions of the first general conductivity type to a source of the transistor.
7. The method of claim 6 , wherein the impurity region of the second general conductivity type and the two impurity regions of the first general conductivity type are circular.
8. A method of manufacturing a semiconductor device, comprising:
providing a single-crystalline semiconductor substrate of a first general conductivity type;
forming a channel layer of a second general conductivity type in the substrate;
forming a circular impurity region of the second general conductivity type in the substrate;
forming a gate electrode in contact with the channel layer with an insulating layer interposed therebetween;
forming a source region of the first general conductivity type in the channel layer adjacent the gate electrode;
forming two circular impurity regions of the first general conductivity type in the circular impurity region of the second general conductivity type so as to be concentric with the circular impurity region of the second general conductivity type;
forming a source electrode so as to be connected to the source region and one of the two circular impurity regions of the first general conductivity type; and
forming a gate pad electrode so as to be connected to the gate electrode and another of the two circular impurity regions of the first general conductivity type.
9. A method of manufacturing a semiconductor device, comprising:
providing a single-crystalline semiconductor substrate of a first general conductivity type;
forming a channel layer of a second general conductivity type in the substrate;
forming a circular impurity region of the second general conductivity type in the substrate;
forming a trench penetrating the channel layer and reaching the semiconductor substrate;
covering an inner wall of the trench with an insulating film;
forming a gate electrode in the trench covered with the insulating film;
forming a source region of the first general conductivity type in the channel layer adjacent the trench;
forming a first circular impurity region of the first general conductivity type in the circular impurity region of the second general conductivity type so as to be concentric with the circular impurity region of the second general conductivity type;
forming a second circular impurity region of the first general conductivity type in the circular impurity region of the second general conductivity type so as to be concentric with the circular impurity region of the second general conductivity type and to be disposed outside the first circular impurity region of the first general conductivity type;
forming a gate pad electrode so as to be connected to the gate electrode and the first circular impurity region of the first general conductivity type; and
forming a source electrode so as to be connected to the source region and the second circular impurity region of the first general conductivity type.
10. The method of claim 8 , wherein the channel layer and the circular impurity region of the second general conductivity type are formed in the substrate in the same process step.
11. The method of claim 9 , wherein the channel layer and the circular impurity region of the second general conductivity type are formed in the substrate in the same process step.
12. The method of claim 8 , wherein the source region and the two circular impurity regions of the first general conductivity type are formed in the same process step.
13. The method of claim 9 , wherein the source region and the first and second circular impurity regions of the first general conductivity type are formed in the same process step.
14. The method of claim 9 , wherein the formation of the circular impurity region comprises forming a plurality of circular and concentric sub-regions of the second general conductivity type separated from each other, the first circular impurity region is formed in the most inner sub-region, and the second circular impurity region is formed in the most outer sub-region.