Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening K 3 to form a P-type impurity region, using a third photoresist as a mask. Then a fourth photoresist is formed on a silicon oxide film to have fourth openings K 4 (phosphorus ion implantation regions) that partially overlap the P-type impurity region. Phosphorus ions (P+) are implanted into the surface of the epitaxial layer in etched-off regions using the fourth photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After that, a P-type upper isolation region is formed in the epitaxial layer by thermal diffusion so that the upper isolation region and a lower isolation region are combined together to make an isolation region.
1. A semiconductor device comprising:
a semiconductor substrate of a first general conductivity type;
a semiconductor layer of a second general conductivity type disposed on the semiconductor substrate;
an isolation region of the first general conductivity type formed in the semiconductor layer so as to surround and electrically isolate a portion of the semiconductor layer;
a first depressed portion and a second depressed portion that are formed in the semiconductor layer of the second general conductivity type so as to be adjacent to the isolation region of the first general conductivity type but not in direct contact with the isolation region, the first depressed portion being disposed on one side of the isolation region, and the second depressed portion being disposed on another side of the isolation region,
wherein a width of an upper end of the isolation region and a width of a lower end of the isolation region are smaller than a width of a center of the isolation region, and
the first depressed portion and the second depressed portion include no metal wiring.
2. The semiconductor device of claim 1 , further comprising a semiconductor element disposed in the semiconductor layer.
3. The semiconductor device of claim 2 , wherein the first depressed portion is formed between the isolation region and the semiconductor element.
4. The semiconductor device of claim 2 , wherein the semiconductor element comprises a bipolar transistor and the semiconductor layer is configured to operate as a collector.
5. The semiconductor device of claim 1 , wherein the width of the center of the isolation region is smaller than a distance between the first depressed portion and the second depressed portion.
6. The semiconductor device of claim 1 , further comprising a buried layer of the second general conductivity type disposed between the semiconductor substrate and the semiconductor layer.
7. The semiconductor device of claim 1 , wherein the isolation region is of a square shape in plan view.
8. The semiconductor device of claim 3 , further comprising a buried layer of the second general conductivity type disposed between the semiconductor substrate and the semiconductor layer, and wherein, in a sectional view of the semiconductor device, a lateral length of the buried layer is smaller than a distance between two sections of the first depressed portion.