Output buffer circuit

1. An output buffer circuit outputting an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage, the output buffer circuit comprising:

an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage;

a first driving circuit outputting a first control signal to control the pull-down transistor;

a second driving circuit including a latch circuit to latch signals, and outputting a second control signal to control the pull-up transistor based on retained data in that latch circuit; and

a level shifter changing the retained data in the latch circuit when logic of the input signal changes,

the level shifter comprising:

an inverter circuit inputting a pulse signal and outputting the inverted signal; and

an n-type MOS transistor having a drain coupled to a data retaining node in the latch circuit, a source to which an output signal from the inverter circuit is input, and a gate to which the first power supply voltage is supplied.

2. The output buffer circuit according to claim 1 , wherein

the second driving circuit is driven by the first power supply voltage with the second power supply voltage as a reference, and

the first driving circuit is driven by the first power supply voltage with a ground voltage as a reference.

3. The output buffer circuit according to claim 1 , further comprising:

a pulse-signal generation circuit generating the pulse signal that rises when logic of the input signal changes.

4. The output buffer circuit according to claim 3 , wherein

the second driving circuit is driven by the first power supply voltage with the second power supply voltage as a reference, and

the first driving circuit is driven by the first power supply voltage with a ground voltage as a reference.

5. The output buffer circuit according to claim 1 , further comprising:

a step-down circuit generating a third voltage resulting from reduction of the second power supply voltage by a predetermined voltage,

wherein the second driving circuit is driven by the second power supply voltage and the third voltage.

6. The output buffer circuit according to claim 1 , further comprising:

a pulse-signal generation circuit generating a pulse signal that rises when logic of the input signal changes,

wherein the level shifter is configured to input the pulse signal to a data retaining node in the latch circuit.

7. An output buffer circuit outputting an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage, the output buffer circuit comprising:

an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage;

a first driving circuit outputting a first control signal to control the pull-down transistor;

a second driving circuit including a latch circuit to latch signals, and outputting a second control signal to control the pull-up transistor based on retained data in that latch circuit; and

a level shifter changing the retained data in the latch circuit when logic of the input signal changes,

the second driving circuit comprising:

a first conductivity type transistor forming a current path between a first data retaining node in the latch circuit and a control terminal of the pull-up transistor and having a control terminal coupled to a second data retaining node in the latch circuit; and

a second conductivity type transistor forming a current path between the second power supply voltage and the control terminal of the pull-up transistor and having a control terminal coupled to the second data retaining node.

8. The output buffer circuit according to claim 7 , wherein

the second driving circuit is driven by the first power supply voltage with the second power supply voltage as a reference, and

the first driving circuit is driven by the first power supply voltage with a ground voltage as a reference.

9. The output buffer circuit according to claim 7 , wherein the level shifter comprising:

an inverter circuit inputting a pulse signal and outputting the inverted signal; and

an n-type MOS transistor having a drain coupled to a data retaining node in the latch circuit, a source to which an output signal from the inverter circuit is input, and a gate to which the first power supply voltage is supplied.

10. The output buffer circuit according to claim 7 , further comprising:

a pulse-signal generation circuit generating a pulse signal that rises when logic of the input signal changes.

11. The output buffer circuit according to claim 10 , wherein the level shifter comprising:

an inverter circuit inputting the pulse signal and outputting the inverted signal; and

an n-type MOS transistor having a drain coupled to a data retaining node in the latch circuit, a source to which an output signal from the inverter circuit is input, and a gate to which the first power supply voltage is supplied.

12. The output buffer circuit according to claim 11 , wherein

the second driving circuit is driven by the first power supply voltage with the second power supply voltage as a reference; and

the first driving circuit is driven by the first power supply voltage with a ground voltage as a reference.

13. The output buffer circuit according to claim 7 , further comprising:

a step-down circuit generating a third voltage resulting from reduction of the second power supply voltage by a predetermined voltage,

wherein the second driving circuit is driven by the second power supply voltage and the third voltage.