Granted Patent B2

US 8,230,263 · App. 12/212,736 · Granted Jul 24, 2012

Abstract

Claims (37)

1. A method comprising:

generating a first code;

applying one or more constraint constructs to said first code;

generating a coverage code and a second code in response to applying said constraint constructs to said first code;

generating a third code in response to said first code;

generating one or more assembly language tests in response to said second code; and

converting said constraint constructs into a code checker.

2. The method according to claim 1 , further comprising the step of:

generating an intermediate test file.

3. The method according to claim 1 , wherein said third code comprises C code used in C reference models.

4. The method according to claim 1 , wherein said coverage code is compiled and run with a RTL compiler.

5. The method according to claim 1 , wherein said second code comprises a set of verilog code.

6. The method according to claim 1 , wherein said coverage code comprises an automatic and a manual set of coverage code.

7. The method according to claim 1 , wherein said one or more assembly language tests are written by a SPARC assembly language translator.

8. An apparatus comprising:

means for generating a first code;

means for applying one or more constraint constructs to said first code;

means for generating a coverage code and a second code in response to applying said constraint constructs to said first code;

means for generating a third code in response to said first code;

means for generating one or more assembly language tests in response to said second code, wherein said apparatus is configured to process video subsystem level constraints;

means for converting said constraint constructs into a code checker; and

circuitry means for storing said one or more assembly language tests.

9. An apparatus comprising:

a first circuit configured to generate a first code;

a second circuit configured to (i) apply one or more constraint constructs to said first code and (ii) generate a coverage code and a second code in response to applying said constraint constructs to said first code;

a third circuit configured to generate a third code in response to said first code;

a fourth circuit configured to generate one or more assembly language tests in response to said second code, wherein said apparatus is configured to process video subsystem level constraints; and

a fifth circuit configured to convert said constraint constructs into a code checker.

10. The apparatus according to claim 9 , wherein said first circuit comprises (i) a parser/translator and (ii) a set of architecture specifications.

11. The apparatus according to claim 10 , wherein said set of architecture specifications includes a set of register specifications and a set of constraint specifications.

12. The apparatus according to claim 10 , wherein said parser/translator is configured to (i) read text documents and (ii) automatically create instances of register files.

13. The apparatus according to claim 9 , wherein said second circuit is further configured to automatically generate (i) one or more register file headers and (ii) module headers in response to said code.

14. The apparatus according to claim 9 , wherein said second circuit is further configured to store one or more base class definitions.

15. The apparatus according to claim 14 , wherein said base class definitions include Field, register, Register File, Sub-module, Module, Sub-system, and System.

16. The apparatus according to claim 9 , wherein said second circuit is further configured to store a constraint library.

17. The apparatus according to claim 9 , wherein said coverage code comprises an automatic and a manual set of coverage code.

18. The apparatus according to claim 9 , wherein said one or more assembly language tests are written by a SPARC assembly language translator.

Assignments (8)