Implementation structure of semiconductor package
An implementation structure of a semiconductor package includes: a printed wiring board which has via-holes piercing a mounted surface and an opposite surface of the printed wiring board; a via-land which is formed on the opposite surface so as to cover openings of the via-holes on the opposite surface and which is conductively connected to the via-holes; a semiconductor chip which has bumps; and a thermosetting adhesive filled between the semiconductor chip and the mounted surface of the printed wiring board, wherein an anisotropic conductive material is filled inside the via-holes, the bumps are inserted into the via-holes, and the bumps are conductively connected to the via-holes via the conductive particles.
1 . An implementation structure of a semiconductor package comprising:
a printed wiring board having a via-hole which pierces a mounted surface and an opposite surface of the printed wiring board;
a via-land which is formed on the opposite surface of the printed wiring board while covering an opening portion of the via-hole and which is conductively connected to the via-hole;
a semiconductor chip which has a bump for being implemented on the mounted surface; and
an adhesive filled between the semiconductor chip and the mounted surface of the printed wiring board, wherein
an anisotropic conductive material made from an conductive particle and an insulating resin is filled in the via-hole, the bump is inserted into the via-hole, and the bump and the via-hole are conductively connected via the conductive particle.
2 . An implementation structure of a semiconductor package according to claim 1 , wherein the conductive particle conductively connects a top of the bump to the via-land.
3 . An implementation structure of a semiconductor package according to claim 1 , wherein the via-hole comprises a conductive portion which is conductively connected to the via-land, wherein the conductive portion is conductively connected to a side portion of the bump via the conductive particle.
4 . An implementation structure of a semiconductor package according to claim 1 , wherein the via-hole comprises a conductive portion which conductively touches a side portion of the bump.
5 . An implementation structure of a semiconductor package according to claim 1 , wherein a diameter of the bump is smaller than a diameter of the via-hole.
6 . An implementation structure of a semiconductor package according to claim 1 , wherein a height of the bump is larger than a depth of the via-hole.
7 . An implementation structure of a semiconductor package according to claim 1 , wherein both a coefficient of linear thermal expansion of the adhesive and a coefficient of linear thermal expansion of an insulating resin included in the anisotropic conductive material are between a coefficient of linear thermal expansion of the semiconductor chip and a coefficient of linear thermal expansion of the printed wiring board.
8 . An implementation method of a semiconductor package comprising the steps of:
filling an anisotropic conductive material inside via-holes which pierce a printed wiring board;
supplying a thermosetting adhesive on a mounted surface of the printed wiring board;
mounting a semiconductor chip on the printed wiring board while inserting the bumps into the via-holes;
pressing at least one of the semiconductor chip and the printed wiring board; and
heating at least one of the semiconductor chip and the printed wiring board.