Test circuit and test method
In a test circuit, a first N-channel transistor with an open drain is connected to a receiver in a test target integrated circuit and is configured to generate a first amplitude voltage signal in response to a first voltage drive signal. A second N-channel transistor with an open drain is connected to the receiver in the test target integrated circuit and is configured to generate a second amplitude voltage signal in response to a second voltage drive signal complimentary to the first voltage drive signal.
1 . A test circuit comprising:
a first N-channel transistor with an open drain, connected to a receiver in a test target integrated circuit and configured to generate a first amplitude voltage signal in response to a first voltage drive signal; and
a second N-channel transistor with an open drain, connected to said receiver in said test target integrated circuit and configured to generate a second amplitude voltage signal in response to a second voltage drive signal complimentary to the first voltage drive signal.
2 . The test circuit according to claim 1 , wherein the first and second amplitude voltage signals are generated based on drive currents from said receiver in said test target integrated circuit.
3 . The test circuit according to claim 2 , wherein said receiver comprises a voltage amplifier circuit configured to amplify a differential voltage signal between the first and second amplitude voltage signals.
4 . The test circuit according to claim 3 , wherein when the first voltage drive signal is in a first voltage level and the second voltage drive signal is in a second voltage level, said voltage amplifier circuit outputs a signal with the first voltage level.
5 . The test circuit according to claim 1 , wherein one of the first and second amplitude voltage signals is an amplitude signal of 100 mV.
6 . The test circuit according to claim 2 , wherein said first and second N-channel transistors are provided in said test target integrated circuit.
7 . The test circuit according to claim 2 , wherein said first and second N-channel transistors are provided in a circuit externally added to a test card.
8 . The test circuit according to claim 1 , wherein said first and second voltage drive signals are supplied from a tester.
9 . A test method of a test target integrated circuit by a tester, comprising:
generating first and second voltage drive signals which are complimentary; and
generating first and second amplitude voltage signals in response to the first and second voltage drive signals, by using first and second N-channel transistors with an open drain, respectively.
10 . The test method according to claim 9 , wherein said generating first and second amplitude voltage signals comprises:
generating the first and second amplitude voltage signals based on drive currents supplied from a receiver in said test target integrated circuit.
11 . The test method according to claim 10 , further comprising:
generating a test output signal by amplifying a differential voltage signal between the first and second amplitude voltage signals.
12 . The test method according to claim 11 , wherein said generating a test output signal comprises:
generating the test output signal with a first voltage level, when the first voltage drive signal is in the first voltage level and the second voltage drive signal is in a second voltage level.
13 . The test method according to claim 9 , wherein said generating first and second voltage drive signals comprises:
generating the first and second voltage drive signals in said tester, and
said generating first and second amplitude voltage signals comprises:
generating the first and second amplitude voltage signals in a test card to supply to said test target integrated circuit.
14 . The test method according to claim 9 , wherein said generating first and second voltage drive signals comprises:
generating the first and second voltage drive signals in said tester, and
said generating first and second amplitude voltage signals comprises:
generating the first and second amplitude voltage signals in said test target integrated circuit to supply to said test target integrated circuit through a test card.
15 . The test method according to claim 9 , wherein said first and second voltage drive signals are supplied from a tester.