Layout correcting method for semiconductor integrated circuit and layout correcting device for semiconductor integrated circuit
A layout correction method, which minimize influence of changing a dummy metal on timings when signal wirings are corrected after completion of arrangement design of wirings including dummy metals, includes the steps of correcting, on a layout of a semiconductor integrated circuit in which at least signal wirings and a dummy metal are arranged, the signal wirings by ignoring the dummy metal, checking a wiring error between the dummy metal and the signal wirings corrected by ignoring the dummy metal, removing the dummy metal that causes the wiring error if the wiring error is found, and embedding another dummy metal after the dummy metal is removed.
1 . A layout correcting method for a layout of a semiconductor integrated circuit in which a wiring and a dummy metal are arranged, the method comprising:
correcting the wiring without changing the dummy metal;
checking a wiring error between the dummy metal and the corrected wiring;
removing the dummy metal that causes the wiring error when the wiring error is found; and
placing a dummy metal other than the removed dummy metal.
2 . The layout correcting method for the semiconductor integrated circuit according to claim 1 , wherein the wiring is a signal wiring.
3 . The layout correcting method for the semiconductor integrated circuit according to claim 2 , wherein the step of placing a dummy metal other than the removed dummy metal includes placing a dummy metal other than the removed dummy metal in a space generated by removing the dummy metal that causes the wiring error, based on a wiring rule.
4 . The layout correcting method for the semiconductor integrated circuit according to claim 3 , wherein the wiring is formed on the same wiring layer as the dummy metal.
5 . A computer readable medium storing a program executed by a computer for performing a layout correction method for a semiconductor integrated circuit in which a wiring and a dummy metal are arranged, the layout correction method comprising:
correcting the wiring without changing the dummy metal;
checking a wiring error between the dummy metal and the corrected wiring;
removing the dummy metal that causes the wiring error when the wiring error is found; and
placing a dummy metal other than the removed dummy metal.
6 . The computer readable medium storing the program according to claim 5 , wherein the wiring is a signal wiring.
7 . The computer readable medium storing the program according to claim 6 , wherein the step of placing a dummy metal includes placing a dummy metal other than the removed dummy metal in a region obtained by the step of removing the dummy metal, based on a wiring rule.
8 . A layout correcting device for a semiconductor integrated circuit in which a signal wiring and dummy metal are arranged, the layout correcting device comprising:
a signal wiring correcting portion for correcting the signal wiring without changing the dummy metal;
a wiring error detecting portion for checking a wiring error between the dummy metal and the corrected signal wiring;
an error dummy metal removing portion for removing the dummy metal that causes the wiring error when the wiring error is found; and
a dummy metal placing portion for embedding another dummy metal after the dummy metal is removed.