Manufacture of devices including solder bumps
View Patent ↗Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.
1. A method for manufacturing an integrated device and a test structure for characterizing properties of the integrated device, the method comprising:
(a) manufacturing the integrated device comprising (i) a substrate, (ii) a pad having a periphery, the pad overlying the substrate to form a pad-substrate interface, (iii) a solder mask overlying the substrate, the solder mask having an opening with a periphery, wherein the periphery of the pad is within the periphery of the opening, and (iv) a solder bump attached to the pad to form a solder-pad interface; and
(b) manufacturing the test structure comprising (i) a substrate, (ii) a pad corresponding to the pad of the integrated device and having a periphery, the pad overlying the substrate to form a pad-substrate interface, (iii) a solder mask overlying the substrate, the solder mask having an opening with a periphery, wherein the periphery of the pad extends below the solder mask and beyond the periphery of the opening, and (iv) a solder bump attached to the pad, wherein:
extending the periphery of the pad of the test structure below the solder mask and beyond the periphery of the opening strengthens the pad-substrate interface of the pad of the test structure compared to the pad-substrate interface of the pad of integrated device; and
the integrated device and the test structure are part of a single manufacturing lot.
2. The method of claim 1 , further comprising:
(c) performing testing on the solder bump of the test device to characterize properties of the solder-pad interface of the integrated device.
3. The method of claim 2 , wherein the testing includes stress testing.