IP Library › Granted Patent US 7,754,538
Granted Patent B2
US 7,754,538 · App. 12/222,336 · Granted Jul 13, 2010

Packaging substrate structure with electronic components embedded therein and method for manufacturing the same

Assignee: Phoenix Precision Technology Corporation
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Quick Facts
Patent No.
US 7,754,538
App. No.
12/222,336
Granted
Jul 13, 2010
Kind
B2
Abstract

A packaging substrate structure with electronic components embedded therein and a method for manufacturing the same are disclosed. The packaging substrate structure comprises: a core board; a built-up structure disposed on at least one surface of the core board, wherein the built-up structure has a plurality of conductive pads and an electronic component-disposing part on the surface thereof; a solder mask disposed on the surface of the built-up structure, where the solder mask has a open area to expose the electronic component-disposing part and a plurality of openings to expose the conductive pads of the built-up structure; and an electronic component disposed on the electronic component-disposing part and in the open area. Accordingly, the packaging substrate disclosed by the present invention exhibits enhanced electrical performance and product reliability.

Claims (8)

1. A method for manufacturing a packaging substrate structure with electronic components embedded therein, comprising:

providing a core board;

forming a built-up structure on at least one surface of the core board, wherein the built-up structure comprises at least one dielectric layer, at least one wiring layer stacked on the dielectric layer, and a plurality of conductive vias electrically connecting to the wiring layer, the built-up structure has an electronic component-disposing part on the surface thereof, and the outmost wiring layer of the built-up structure has a plurality of conductive pads and a metal block on the electronic component-disposing part;

forming a solder mask on the surface of the built-up structure, wherein a plurality of openings are formed in the solder mask to expose the conductive pads of the built-up structure, also a first open area is formed in the solder mask to expose the metal block, and a second open area is formed by etching the metal block; and

placing an electronic component in the first and second open areas, wherein the electronic component has an active surface and an inactive surface, the active surface has a plurality of electrode pads, and the inactive surface faces the electronic component-disposing part of the built-up structure.

2. The method as claimed in claim 1 , wherein the exposed part of the metal block is etched to form the second open area while the unexposed part of the metal block is used as a heat sink around the second open area.

3. The method as claimed in claim 1 , wherein the inactive surface of the electronic component is attached to the electronic component-disposing part of the built-up structure through an adhesive layer.

4. The method as claimed in claim 1 , further comprising filling a gap between the first and second open areas and the electronic component with an adhesive material to fix the electronic component.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2008
From: HSU, SHIH-PING
To: PHOENIX PRECISION TECHNOLOGY CORPORATION
Reel/Frame 021407/0790 →
Priority Claims (1)
TW 096130123 · Aug 15, 2007 · national
Continuity (1)
Related Publication 20090046432A1 · Feb 19, 2009