IP Library Granted Patent US 9,236,448
Granted Patent B2
US 9,236,448 · App. 12/231,369 · Granted Jan 12, 2016

Method for achieving very small feature size in semiconductor device by undertaking silicide sidewall growth and etching

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Quick Facts
Patent No.
US 9,236,448
App. No.
12/231,369
Granted
Jan 12, 2016
Kind
B2
Abstract

In the present method of fabricating a semiconductor device, initially, a semiconductor substrate is provided. An oxide layer is provided on and in contact with the substrate, and a polysilicon layer is provided on and in contact with the oxide layer. A layer of photoresist is provided on the polysilicon layer, and the photoresist is patterned to provide a photoresist body, which is used as a mask to etch away polysilicon and oxide, forming a polysilicon element thereunder. The photoresist body is then removed. A nickel layer is provided on the resulting structure, and a reaction step is undertaken to provide that nickel diffuses into the exposed top and side portions of the polysilicon body, forming nickel silicide. After the reaction step, the remaining nickel is removed, and a chemical-mechanical polishing step is undertaken to remove nickel silicide so that a pair of nickel silicide bodies remain, separated by polysilicon. Using the nickel silicide bodies as masks, the polysilicon and oxide thereunder are etched away.

Claims (41)

1. A method of fabricating an electronic device comprising:

providing a structure over an insulating layer and a substrate, the structure comprising a first body comprising a polysilicon and a second body comprising polysilicon reacted with at least some nickel from a nickel layer disposed over the first body, the second body comprising first, second, and third portions, the first portion being disposed between the second and third portions;

removing the first portion of the second body, with at least a part of the second and third portions of the second body remaining; and

removing an area of the first body using the second and third portions of the second body as a mask over a remaining area of the first body,

wherein a side surface of the second portion is vertically aligned with a side surface of the first body and a side surface of the third portion is vertically aligned with an opposite side surface of the first body,

further wherein a bottom surface of each of the second portion and the third portion is lower than a bottom surface of the first portion.

2. The method of claim 1 wherein the material of the first body is removed by etching.

3. The method of claim 1 wherein the first portion of the second body is removed by chemical-mechanical polishing.

4. The method of claim 1 wherein the second body is in contact with the first body.

5. The method of claim 1 wherein the material of the first body is removed by etching.

6. The method of claim 5 wherein the first portion of the second body is removed by chemical-mechanical polishing.

7. The method of claim 1 , wherein the first portion of the second body is disposed over the first body, the second portion of the second body extends into a first side of the first body and the third portion of the second body extends into a second side of the first body on a side opposite to the first side.

8. The method of claim 7 wherein the first body is polysilicon.

9. The method of claim 7 wherein the second body is a silicide.

10. The method of claim 1 , wherein the second body is formed by providing a nickel layer over a polysilicon, and performing a reaction step to diffuse nickel of the nickel layer into exposed top and side portions of the polysilicon to form the first and second portions of the second body.

11. The method of claim 10 , wherein the performing the reaction step comprises forming the second body as a nickel silicide with the first portion comprising a top portion of nickel silicide disposed over the first body, and the second portion comprising a side portion of nickel silicide disposed as a side portion extending into the first body.

12. The method of claim 11 , wherein the removing the first portion of the second body comprises removing the top portion of nickel silicide such that the side portion of nickel silicide remains.

13. The method of claim 1 , wherein the first portion of the second body comprises material from the nickel layer that is unreactant with the first body.

14. The method of claim 1 , wherein the diffusing the layer into exposed surfaces of the first body and causing a reaction to portions of the first body is performed inwardly from an exposed top surface and exposed side surfaces of the first body.

15. A method of fabricating a semiconductor device comprising:

providing a substrate;

providing an insulating layer on and in contact with the substrate;

providing a first body on and in contact with the insulating layer;

providing a nickel layer over and in contact with the first body;

forming a second body from the nickel layer and the first body by reacting at least some of the nickel layer with the first body, the second body comprising first, second and third portions, the first portion being between the second and third portions, the second and third portions being vertically aligned with separate side surfaces of the first body and having bottom surfaces lower than a bottom surface of the first portion;

removing the un-reacted nickel;

removing the first portion of the second body, with at least parts of the second and third portions of the second body remaining; and

removing a first portion of the first body using the second and third portions of the second body as a mask over a remaining second portion of the first body.

16. The method of claim 15 and further comprising forming a doped region in the substrate.

17. The method of claim 15 and further comprising removing material of the insulating layer using the second and third portions of the second body as a mask, to expose a portion of the substrate.

18. The method of claim 17 wherein the material of the first body and the material of the insulating layer are removed by etching.

19. The method of claim 17 and further comprising forming a doped region in the exposed portion of the substrate.

20. The method of claims 19 wherein the doped region is formed by implantation.

21. The method of claim 15 wherein the first body is polysilicon.

22. The method of claim 21 wherein the second body is a silicide.

23. The method of claim 22 wherein the silicide is NiSi silicide.

24. The method of claim 15 , wherein the second body is formed by providing a nickel layer over the structure, and performing a reaction step to diffuse nickel of the nickel layer into exposed top and side portions of the polysilicon to form the first, second, and third portions of the second body.

25. The method of claim 24 , wherein the performing the reaction step comprises forming the second body as a nickel silicide with the first portion comprising a top portion of nickel silicide disposed over the first body, and the second and third portions comprising side portions of nickel silicide disposed as side portions extending into the first body.

26. The method of claim 25 , wherein the removing the first portion of the second body comprises removing the top portion of nickel silicide such that the side portions of nickel silicide remains.

27. The method of claim 15 , wherein the first portion of the second body comprises material from the layer that is unreactant with the first body.

28. The method of claim 15 , wherein the forming of the second body comprises diffusing the nickel layer inwardly from an exposed top surface and exposed side surfaces of the first body.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035856/0527 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
SECURITY AGREEMENT Recorded Aug 23, 2012
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 028837/0076 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2008
From: KIM, EUNHA; NGO, MINH-VAN
To: SPANSION LLC
Reel/Frame 021522/0205 →