IP Library Patent Application 12232006
Patent Application
App. No. 12/232,006

Semiconductor device having silicon-on-insulator (SOI) structure and method of forming semiconductor device

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Quick Facts
Patent No.
US None
App. No.
12/232,006
Abstract

A semiconductor device includes a substrate, an insulating layer formed on the substrate, an active layer formed on the insulating layer, and a metal layer formed on a back surface of the substrate, the substrate and the metal layer being in ohmic contact. By bringing the substrate and the metal layer into ohmic contact, the resistance difference between the substrate and the metal layer can be reduced.

Claims (57)

1 . A semiconductor device, comprising:

a substrate;

an insulating layer formed on the substrate;

an active layer formed on the insulating layer; and

a metal layer formed on a back surface of the substrate, the metal layer being in ohmic contact with the substrate.

2 . The semiconductor device according to claim 1 , wherein an impurity concentration of the substrate is 1×10 18 cm −3 or higher.

3 . The semiconductor device according to claim 2 , wherein:

the active layer comprises:

an active region; and

a high concentration region whose impurity concentration is higher than that in the active region, and being formed on the active layer in contact with the insulating layer.

4 . The semiconductor device according to claim 2 , wherein:

the active layer has a trench which reaches the insulating film; and

an insulating layer is formed in the trench.

5 . The semiconductor device according to claim 1 , wherein:

the substrate includes:

a high concentration layer, whose an impurity concentration is 1×10 18 cm −3 or higher, being in contact with the metal layer, and

a low concentration layer formed on the high concentration layer, the low concentration having an impurity concentration which is lower than that of the high concentration layer.

6 . The semiconductor device according to claim 5 , wherein

an impurity concentration of the low concentration layer is in a range of 1×10 14 cm −3 to 1×10 16 cm −3 .

7 . The semiconductor device according to claim 5 , wherein the impurity concentration of the high concentration layer is 1×10 19 cm −3 or higher.

8 . A method of manufacturing a semiconductor device, comprising:

forming an insulating layer on a first surface of a substrate whose impurity concentration is 1×10 18 cm −3 or higher;

forming an active layer on the insulating layer; and

forming a metal layer on a second surface of the substrate opposite to the first surface of the substrate so that the metal layer and the substrate are in ohmic contact.

9 . The method according to claim 8 , wherein

the substrate and the active layer are bonded with the insulating layer therebetween, and

impurities are diffused in the active layer by heat treatment.

10 . The method according to claim 8 , wherein the insulating layer and the active layer are formed by:

oxidizing the active layer to form the insulating layer on a surface of the active layer;

bonding the active layer, formed with the insulating layer, and the substrate; and

polishing the insulating layer until the active layer is exposed on a surface opposite to a surface to which the active layer is bonded.

11 . The method according to claim 8 , wherein the insulating layer and the substrate are formed by:

oxidizing the substrate to form the insulating layer on a surface of the substrate;

bonding the substrate, formed with the insulating layer, and the active layer, and removing an insulating film of the substrate; and

polishing the active layer from a surface opposite to a surface to which the active layer is bonded.

12 . The method according to claim 8 , wherein

the substrate is implanted with impurities to have a high concentration layer having the impurity concentration of 1×10 18 cm −3 or higher while leaving a low concentration layer whose impurity concentration is lower than that of the high concentration layer; and

the metal layer is formed on the high concentration layer.

13 . The method according to claim 12 , wherein the insulating layer and the active layer are formed by:

oxidizing the active layer to form the insulating layer on a surface of the active layer;

bonding the active layer, formed with the insulating layer, and the low concentration substrate; and

polishing the insulating layer until the active layer is exposed on a surface of the insulating layer opposite to a surface to which the active layer is bonded.

14 . The method according to claim 12 , wherein the insulating layer and the substrate are formed by:

oxidizing the substrate to form the insulating layer on a surface of the substrate;

bonding the substrate, formed with the insulating layer, and the active layer; and

polishing the active layer from a surface opposite to a surface to which the active layer is bonded.

15 . The method according to claim 12 , wherein

an impurity concentration of the low concentration layer is in a range of 1×10 14 cm −3 to 1×10 16 cm −3 .

16 . The method according to claim 12 , wherein the impurity concentration of the high concentration layer is 1×10 19 cm −3 or higher.

17 . A semiconductor device, comprising:

a semiconductor substrate whose impurity concentration is in a range of 1×10 14 cm −3 to 1×10 16 cm −3 ;

an insulating layer substantially entirely formed on a first surface of said semiconductor substrate;

an active layer formed on said insulating layer to constitute a silicon-on-insulator structure with said insulating layer;

an impurity layer substantially entirely formed on a second surface of said semiconductor substrate, said first surface being opposite to said second surface, said impurity layer having an impurity concentration being 1×10 18 cm −3 or higher; and

a metal layer formed on said impurity layer.

18 . The semiconductor device as claimed in claim 17 , further comprising:

an insulator formed in said active layer to divide said active layer into a plurality of active layers.

Assignments (2)
CHANGE OF NAME Recorded Oct 28, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025214/0687 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2008
From: TAKAO, NORIYUKI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 021564/0466 →