IP Library Granted Patent US 8,156,640
Granted Patent B2
US 8,156,640 · App. 12/245,729 · Granted Apr 17, 2012

Substantially continuous layer of embedded transient protection for printed circuit boards

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Quick Facts
Patent No.
US 8,156,640
App. No.
12/245,729
Granted
Apr 17, 2012
Kind
B2
Abstract

The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.

Claims (30)

1. A method for making a core layer structure for use in PCB manufacturing, the method comprising:

using a first layer of conductive foil;

coating a layer of transient protection material on one surface of the conductive foil;

using one or more layers of B-stage dielectric material to bond said coated first layer of conductive foil on one surface of said one or more layers of B-stage dielectric material with a second layer of conductive foil on the opposing surface.

2. The method as recited in claim 1 , wherein said transient protection material behaves in a bi-directional manner for clamping both positive and negative transients of at least one of current and voltage.

3. The method as recited in claim 1 , further comprising:

bonding said coated conductive foil to at least one surface of a layer of dielectric material to form said core layer structure, wherein said layer of dielectric material is un-reinforced film.

4. The method as recited in claim 1 , further comprising:

bonding said coated conductive foil to at least one surface of a layer of dielectric material to form said core layer structure, wherein said layer of dielectric material is reinforced with fiberglass material of varying composition.

5. A method for making a core layer structure for use in PCB manufacturing, the method comprising:

using a layer of conductive material, said layer of conductive material having a top surface and a bottom surface; and

coating a layer of transient protection material on one of said top surface and said bottom surface.

6. The method as recited in claim 5 , further comprising bonding said coated conductive material to at least one surface of a layer of dielectric material to form said core layer structure.

7. The method as recited in claim 6 , wherein said layer of dielectric material is any one of: epoxy, polyimide, teflon and any nonconducting polymer.

8. The method as recited in claim 6 , wherein said layer of dielectric material is un-reinforced film.

9. The method as recited in claim 6 , wherein said layer of dielectric material is reinforced with fiberglass material of varying composition.

10. The method as recited in claim 6 , wherein said layer of dielectric material is reinforced with random fibers of various compositions.

11. The method as recited in claim 6 , further comprising laminating said core layer structure to a PCB stackup.

12. The method as recited in claim 5 , wherein said layer of conductive material is coated with a resin.

13. The method as recited in claim 12 , wherein said resin is any one of a polyimide and an epoxy polymer.

14. The method as recited in claim 5 , wherein exposed areas of said layer of transient protection material is removed by mechanical methods.

15. The method as recited in claim 5 , wherein said transient protection material behaves in a bi-directional manner for clamping both positive and negative transients of at least one of current and voltage.

16. A method for making a printed circuit board with integrated transient protection, the method comprising:

making said printed circuit board using multiple layers including at least one signal area, and at least one reference plane; and

making said at least one reference plane using transient protection material and at least one layer of conductive material.

17. The method as recited in claim 16 , wherein said transient protection material behaves in a bi-directional manner for clamping both positive and negative transients of at least one of current and voltage.

18. The method as recited in claim 16 , further comprising:

bonding said at least one reference plane to at least one surface of a layer of dielectric material, wherein said layer of dielectric material is un-reinforced film.

19. The method as recited in claim 16 , further comprising:

bonding said at least one reference plane to at least one surface of a layer of dielectric material, wherein said layer of dielectric material is reinforced with fiberglass material of varying composition.

Assignments (4)
SECURITY INTEREST Recorded Oct 28, 2025
From: SANMINA CORPORATION
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 073363/0212 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2019
From: U.S. BANK NATIONAL ASSOCIATION, SOLELY AS NOTES COLLATERAL AGENT
To: SANMINA CORPORATION; HADCO CORPORATION; HADCO SANTA CLARA; SCI TECHNOLOGY; SENSORWISE, INC.
Reel/Frame 049378/0927 →
SECURITY INTEREST Recorded Jun 5, 2014
From: SANMINA CORPORATION, AS GRANTOR; SANMINA CORPORATION, F/K/A SANMINA-SCI CORPORATION, AS GRANTOR; HADCO SANTA CLARA, INC., AS GRANTOR; SCI TECHNOLOGY, INC., AS GRANTOR
To: US BANK NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 033094/0826 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2012
From: DUDNIKOV, GEORGE, JR.; GISIN, FRANZ; SCHROEDER, GREGORY J.
To: SANMINA-SCI CORPORATION
Reel/Frame 027858/0219 →