Semiconductor integrated circuit
View Patent ↗A semiconductor integrated circuit having a low maximum allowable operating frequency such as an analog circuit can be prevented from being destroyed during a scan test. When a scan test mode signal is “1”, output signals of a first AND circuit and a second AND circuit are fixed to a low level and an output of an OR circuit is fixed to a high level. Therefore, output signals of fourth through sixth flip-flops FF 4 -FF 6 are not transferred to first through third analog circuits during the scan test. On the other hand, the output signals of the fourth through sixth flip-flops FF 4 -FF 6 are transferred to the first through third analog circuits during a normal operation.
1. A semiconductor integrated circuit comprising:
a first circuit comprising a plurality of logic circuits;
a plurality of flip-flops each provided for a corresponding logic circuit;
a plurality of selectors connecting the flip-flops to the first circuit in a normal operation, the selectors being configured to connect the flip-flops in a chain formation so that the flip-flops make a shift register during a scan test;
a second circuit having a maximum allowable operating frequency lower than a maximum operating frequency of the shift register during the scan test; and
a gate circuit that receives an output of one of the flip-flops and controls a transfer of the output so that the output is transferred to the second circuit during the normal operation and the output is not transferred to the second circuit during the scan test.
2. The semiconductor integrated circuit of claim 1 , wherein an output of the gate circuit is fixed to a predetermined level during the scan test.
3. The semiconductor integrated circuit of claim 2 , wherein the first circuit comprises a digital circuit, and the second circuit comprises an analog circuit.
4. The semiconductor integrated circuit of claim 3 , wherein the second circuit comprises a level shift circuit.
5. The semiconductor integrated circuit of claim 4 , wherein the first circuit comprises a combinational logic circuit.
6. The semiconductor integrated circuit of claim 3 , wherein the first circuit comprises a combinational logic circuit.
7. The semiconductor integrated circuit of claim 2 , wherein the second circuit comprises a level shift circuit.
8. The semiconductor integrated circuit of claim 7 , wherein the first circuit comprises a combinational logic circuit.
9. The semiconductor integrated circuit of claim 2 , wherein the first circuit comprises a combinational logic circuit.
10. The semiconductor integrated circuit of claim 1 , wherein the first circuit comprises a digital circuit, and the second circuit comprises an analog circuit.
11. The semiconductor integrated circuit of claim 10 , wherein the second circuit comprises a level shift circuit.
12. The semiconductor integrated circuit of claim 11 , wherein the first circuit comprises a combinational logic circuit.
13. The semiconductor integrated circuit of claim 10 , wherein the first circuit comprises a combinational logic circuit.
14. The semiconductor integrated circuit of claim 1 , wherein the second circuit comprises a level shift circuit.
15. The semiconductor integrated circuit of claim 14 , wherein the first circuit comprises a combinational logic circuit.
16. The semiconductor integrated circuit of claim 1 , wherein the first circuit comprises a combinational logic circuit.