Semiconductor integrated circuit with a random number generation circuit wherein the rise and all times are variably controlled
View Patent ↗The invention reduces unnecessary electromagnetic radiation noise associated with a step pulse of an output signal. A random number control register is a register for controlling start, standby, stop, timing or the like of output of random number data from a random number generation circuit. Random number data outputted by the random number generation circuit is stored in a rise/fall time variable data register. The data stored in the rise/fall time variable data register is replaced by random number data sequentially generated by the random number generation circuit. An output circuit is a circuit for outputting a signal from an internal circuit of a microcomputer to an external device, and the rise/fall times of the output signal from the output circuit are variably controlled in response to the random number data stored in the rise/fall time variable data register.
1. A semiconductor integrated circuit comprising:
a random number generation circuit generating random number data; a first control register storing the random number data outputted by the random number generation circuit; and an output circuit outputting an output signal, wherein rise and fall times of the output signal are variably controlled in response to the random number data stored in the first control register; and further comprising a second control register storing control data for controlling ranges of the rise and fall times of the output signal which are variably controlled in response to the random number data stored in the first control register.
2. The semiconductor integrated circuit of claim 1 , wherein the output circuit comprises an output transistor outputting the output signal and a delay circuit delaying a signal applied to an input terminal of the output transistor in response to the random number data stored in the first control register.
3. The semiconductor integrated circuit of claim 2 , wherein the delay circuit comprises a plurality of capacitor elements and a plurality of switching elements switching in response to the random number data stored in the first control register and selectively connecting the capacitor elements to the input terminal of the output transistor.
4. The semiconductor integrated circuit of claim 1 , wherein the output circuit comprises an output transistor outputting the output signal and a delay circuit delaying the output signal in response to the random number data stored in the first control register.
5. The semiconductor integrated circuit of claim 4 , wherein the delay circuit comprises a plurality of capacitor elements and a plurality of switching elements switching in response to the random number data stored in the first control register and selectively connecting the capacitor elements to an output terminal of the output transistor.
6. The semiconductor integrated circuit of claim 1 , wherein the output circuit uses the random number data so that the rise and fall times of the output signal form a normal distribution.