IP Library Granted Patent US 8,212,925
Granted Patent B2
US 8,212,925 · App. 12/249,515 · Granted Jul 3, 2012

Sync separation circuit

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Quick Facts
Patent No.
US 8,212,925
App. No.
12/249,515
Granted
Jul 3, 2012
Kind
B2
Abstract

A sync separation circuit separates a synchronizing signal from a video signal containing the synchronizing signal. A minimum level detecting section detects a minimum level of a video signal. A sync tip level detecting section detects a sync tip level in the video signal. A pedestal level detecting section detects a pedestal level in the video signal. Based on both the sync tip level detected by the sync tip level detecting section and the pedestal level control by the pedestal level detecting section, a slice level setting section sets a slice level corresponding to an intermediate value between the sync tip level and the pedestal level. The slice level control section sets the slice level based on the minimum level detected by the minimum level detecting section if the slice level set based on the sync tip level and the pedestal level is inappropriate.

Claims (9)

1. A sync separation circuit separating a synchronizing signal from a video signal containing the synchronizing signal, the circuit comprising:

a minimum level detecting circuit which detects a minimum level of a video signal;

a sync tip level detecting circuit which detects a sync tip level in the video signal;

a pedestal level detecting circuit which detects a pedestal level in the video signal; and

a slice level control circuit which sets a slice level to an initial slice level corresponding to the minimum level and subsequently, based on the synchronizing signal obtained after sync separation utilizing the initial slice level, detects the sync tip level and the pedestal level and sets the slice level to a subsequent slice level corresponding to an intermediate value between the sync tip level and the pedestal level,

wherein, upon detecting a vertical synchronization signal, the slice level control circuit determines that the subsequent slice level is inappropriate, the slice level control circuit sets the slice level to a new slice level based on the minimum level, and

wherein, upon detecting a vertical synchronization signal, the slice level control circuit determines that the subsequent slice level is appropriate, the slice level control unit sets the slice level to a new slice level corresponding to the subsequent slice level made closer to a target slice level using a predetermined time constant, wherein the target slice level corresponds to an intermediate value between the sync tip level and the pedestal level.

2. The sync separation circuit according to claim 1 , wherein the slice level control circuit sets a new slice level based on the sync tip level and the pedestal level by setting a target slice level based on the detected sync tip level and pedestal level and making the subsequent slice level closer to the target value using a predetermined time constant.

3. The sync separation circuit according to claim 2 , wherein when the currently set slice level is not positioned midway between the detected sync tip level and pedestal level, the slice level control circuit determines the currently set slice level to be inappropriate and adopts the initial slice level corresponding to the minimum level.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2008
From: OKADA, TORU; EBINUMA, HIROYUKI
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 021692/0899 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2008
From: SAKYO, CHIKARA; EBINUMA, HIROYUKI
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 021692/0889 →