Granted Patent B2

US 8,089,490 · App. 12/249,553 · Granted Jan 3, 2012

Abstract

Claims (9)

1. A correction arithmetic circuit comprising:

a lookup table that has stored therein correction data corresponding to input data at predetermined intervals relevant to predetermined higher-order bits of the input data, the lookup table having a plurality of one-port split lookup tables having alternately stored therein the correction data corresponding to the input data;

an address generating unit that generates addresses for the one port split lookup tables from the higher-order bits of the input data, wherein the addresses for the one port split lookup tables are for readout of the correction data before and after the input data; and

an interpolation arithmetic unit that executes interpolation arithmetic with the use of lower-order bits of the input data for the correction data read from the plurality of the split lookup tables through the generated addresses.

2. The correction arithmetic circuit of claim 1 , wherein the input data is video data, and wherein the interpolation arithmetic unit acquires video data after gamma correction.

3. The correction arithmetic circuit of claim 1 , wherein

the lookup table includes two split lookup tables that are a first lookup table having odd-numbered correction data stored therein and a second lookup table having even-numbered correction data stored therein, and wherein

the address generating unit changes whether readout addresses of the first lookup table and the second lookup table are made identical or different depending on a level of the lower-order bits.

4. The correction arithmetic circuit of claim 3 , wherein the input data is video data, and wherein the interpolation arithmetic unit acquires video data after gamma correction.

Assignments (9)