IP Library Granted Patent US 8,421,241
Granted Patent B2
US 8,421,241 · App. 12/259,100 · Granted Apr 16, 2013

System and method for stacking a plurality of electrically coupled semiconductor chips with a conductive pin

Inventors: Kouichi Meghro (Kanagawa, JP); Junichi Kasai (Kanagawa, JP)
Assignee: Spansion LLC
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Quick Facts
Patent No.
US 8,421,241
App. No.
12/259,100
Granted
Apr 16, 2013
Kind
B2
Abstract

The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other.

Claims (27)

1. A semiconductor device comprising:

a semiconductor chip;

a lead frame, electrically coupled to the semiconductor chip, the lead frame provided with a recessed portion on a surface of the lead frame;

a resin section that molds the semiconductor chip and the lead frame, the resin section provided with an opening above the recessed portion of the lead frame;

a hole that penetrates through the lead frame, the hole being disposed in a part of the recessed portion and having a width that is smaller in magnitude than the width of the recessed portion wherein the sidewalls of the opening, the recessed portion and the hole are parallel, and wherein the sidewalls of the opening are formed in the resin section parallel to and outside of the sidewalls of the recessed portion and the hole,

wherein the semiconductor device comprises one of a plurality of semiconductor devices electrically coupled via a conductive pin, the conductive pin being inserted through the recessed portion provided on the lead frame and the opening wherein the opening is wider than the recessed portion and the hole and the opening and the recessed portion comprises unfilled space that surrounds the conductive pin.

2. The semiconductor device according to claim 1 , wherein the recessed portion is provided on an upper surface of the lead frame.

3. The semiconductor device according to claim 1 , wherein the recessed portion is provided on a lower surface of the lead frame.

4. The semiconductor device according to claim 1 , wherein a lower surface of the semiconductor chip is not covered by the resin section.

5. The semiconductor device according to claim 1 , wherein the resin section is formed on the upper surface of the lead frame and the lower surface of the lead frame, and the resin section is provided with an opening above and below the recessed portion.

6. A device comprising:

a plurality of semiconductor devices, a semiconductor device comprising:

a semiconductor chip;

a lead frame, electrically coupled to the semiconductor chip, the lead frame provided with a recessed portion on a surface of the lead frame; and

a resin section that molds the semiconductor chip and the lead frame, the resin section provided with an opening above the recessed portion of the lead frame; and

a conductive pin, the conductive pin being inserted through the recessed portion provided on the lead frame and the opening provided in the resin section of the plurality of semiconductor devices, so as to electrically couple the plurality of semiconductor devices to each other wherein the conductive pin extends through a hole in the lead frame wherein the opening is wider than the recessed portion and the hole and the opening and the recessed portion comprises unfilled space that surrounds the conductive pin and the hole and the recessed portion have widths of different magnitude wherein the sidewalls of the opening, the recessed portion and the hole are parallel, with the sidewalls of the opening formed outside of the sidewalls of the recessed portion and the hole.

7. A semiconductor device according to claim 6 , further comprising:

an interposer mounted with a first semiconductor device of the plurality of semiconductor devices;

an external coupling terminal provided on a surface of the interposer that is opposite to a surface mounted to the first semiconductor device; and

a redistribution layer electrically coupling the first semiconductor device and the external coupling terminal to each other.

8. A method for manufacturing a semiconductor device, the method comprising:

stacking a plurality of semiconductor devices; and

mechanically and electrically coupling the plurality of semiconductor devices to each other by a conductive pin being inserted through a recessed portion provided on a lead frame and an opening provided in a resin section of each of the plurality of semiconductor devices wherein the opening is wider than the recessed portion and the opening and the recessed portion comprises unfilled space that surrounds the conductive pin wherein a hole in the recessed portion has a width of a first magnitude and the recessed portion has a width of a second magnitude with the first magnitude being less than the second magnitude wherein the sidewalls of the opening, the recessed portion and the hole are parallel, with the sidewalls of the opening formed outside of the sidewalls of the recessed portion and the hole.

9. The method for manufacturing a semiconductor device according to claim 8 , wherein a semiconductor device of the plurality of semiconductor devices is manufactured by a method comprising:

forming a recessed portion on an upper surface or a lower surface of a lead frame;

electrically coupling the lead frame and a semiconductor chip to each other; and

forming a resin section that molds the lead frame and the semiconductor chip to form an opening above the recessed portion.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 22, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 044949/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 044938/0360 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036055/0276 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2009
From: MEGHRO, KOUICHI; KASAI, JUNICHI
To: SPANSION LLC
Reel/Frame 022149/0738 →
Priority Claims (1)
JP 2007-277998 · Oct 25, 2007 · national
Continuity (1)
Related Publication 20090289336A1 · Nov 26, 2009