Audio signal processing circuit
View Patent ↗An audio signal processing circuit comprising: a holding circuit configured to receive a clock signal and set data corresponding to the clock signal, and to hold the set data; a processing circuit configured to process at least one of a first audio signal and a second audio signal input in parallel, based on the set data of the holding circuit; and a set data output circuit configured to output the clock signal to the holding circuit based on the first audio signal corresponding to the clock signal, and output the set data to the holding circuit based on the second audio signal corresponding to the set data.
1. An audio signal processing circuit comprising:
a set data output circuit configured to receive a first audio signal and a second audio signal and to generate a clock signal based on the first audio signal and set data based on the second audio signal;
a holding circuit configured to receive the set data in accordance with the clock signal and to hold the set data; and
a processing circuit configured to receive the first audio signal and the second audio signal in parallel and to process at least one of the first audio signal and the second audio signal based on the set data held by the holding circuit.
2. The audio signal processing circuit according to claim 1 , wherein
the processing circuit includes:
a signal processing circuit configured to process at least one of the first audio signal and the second audio signal; and
a setting circuit configured to control an operation of the signal processing circuit based on the set data held by the holding circuit.
3. The audio signal processing circuit according to claim 2 , wherein
the set data output circuit includes:
an output circuit configured to be able to generate the clock signal corresponding to a level of the first audio signal and the set data corresponding to a level of the second audio signal; and
a control circuit configured to control the output circuit so as to output the clock signal and the set data to the holding circuit when a selection signal is at one logic level, and so as not to output the clock signal and the set data to the holding circuit when the selection signal is at the other logic level, the selection signal being a signal that is at the one logic level when the first audio signal corresponds to the clock signal and the second audio signal corresponds to the set data.
4. The audio signal processing circuit according to claim 3 , wherein
the holding circuit is configured to be able to update the set data when an instruction signal to be input is at one logic level, and wherein
the audio signal processing circuit further comprises an update control circuit configured to output the instruction signal of the one logic level when an update control signal is at one logic level, and output the instruction signal of the other logic level when the update control signal is at the other logic level, the update control signal being a signal that is at the one logic level when the first audio signal corresponding to the clock signal is input to the set data output circuit.
5. The audio signal processing circuit according to claim 2 , wherein
the holding circuit holds the set data when address data to be input according to the clock signal matches predetermined address data, and wherein
the set data output circuit outputs the clock signal to the holding circuit based on the first audio signal corresponding to the clock signal, and outputs the address data to the holding circuit based on the second audio signal corresponding to the address data, and thereafter, further outputs the clock signal to the holding circuit based on the first audio signal corresponding to the clock signal, and outputs the set data to the holding circuit based on the second audio signal corresponding to the set data.
6. The audio signal processing circuit according to claim 2 , wherein
the holding circuit is configured to be able to update the set data when an instruction signal to be input is at one logic level, and wherein
the audio signal processing circuit further comprises an update control circuit configured to output the instruction signal of the one logic level when an update control signal is at one logic level, and output the instruction signal of the other logic level when the update control signal is at the other logic level, the update control signal being a signal that is at the one logic level when the first audio signal corresponding to the clock signal is input to the set data output circuit.
7. The audio signal processing circuit according to claim 1 , wherein
the set data output circuit includes:
an output circuit configured to be able to generate the clock signal corresponding to a level of the first audio signal and the set data corresponding to a level of the second audio signal; and
a control circuit configured to control the output circuit so as to output the clock signal and the set data to the holding circuit when a selection signal is at one logic level, and so as not to output the clock signal and the set data to the holding circuit when the selection signal is at the other logic level, the selection signal being a signal that is at the one logic level when the first audio signal corresponds to the clock signal and the second audio signal corresponds to the set data.
8. The audio signal processing circuit according to claim 7 , wherein
the holding circuit holds the set data when address data to be input according to the clock signal matches predetermined address data, and wherein
the set data output circuit outputs the clock signal to the holding circuit based on the first audio signal corresponding to the clock signal, and outputs the address data to the holding circuit based on the second audio signal corresponding to the address data, and thereafter, further outputs the clock signal to the holding circuit based on the first audio signal corresponding to the clock signal, and outputs the set data to the holding circuit based on the second audio signal corresponding to the set data.
9. The audio signal processing circuit according to claim 7 , wherein
the holding circuit is configured to be able to update the set data when an instruction signal to be input is at one logic level, and wherein
the audio signal processing circuit further comprises an update control circuit configured to output the instruction signal of the one logic level when an update control signal is at one logic level, and output the instruction signal of the other logic level when the update control signal is at the other logic level, the update control signal being a signal that is at the one logic level when the first audio signal corresponding to the clock signal is input to the set data output circuit.
10. The audio signal processing circuit according to claim 1 , wherein
the holding circuit holds the set data when address data to be input according to the clock signal matches predetermined address data, and wherein
the set data output circuit outputs the clock signal to the holding circuit based on the first audio signal corresponding to the clock signal, and outputs the address data to the holding circuit based on the second audio signal corresponding to the address data, and thereafter, further outputs the clock signal to the holding circuit based on the first audio signal corresponding to the clock signal, and outputs the set data to the holding circuit based on the second audio signal corresponding to the set data.
11. The audio signal processing circuit according to claim 1 , wherein
the holding circuit is configured to be able to update the set data when an instruction signal to be input is at one logic level, and wherein
the audio signal processing circuit further comprises an update control circuit configured to output the instruction signal of the one logic level when an update control signal is at one logic level, and output the instruction signal of the other logic level when the update control signal is at the other logic level, the update control signal being a signal that is at the one logic level when the first audio signal corresponding to the clock signal is input to the set data output circuit.