Variability-aware scheme for high-performance asynchronous circuit voltage regulation
View Patent ↗A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
1. A system for regulating voltage to a plurality of circuit elements in a datapath to maximize power efficiency in a desynchronized circuit, the system, comprising:
a first controller circuit, the first controller circuit comprising at least a first pulsed latch enable signal, a request signal output and an acknowledge signal input;
a second controller circuit, the second controller circuit comprising at least second pulsed latch enable signal, a request signal input and an acknowledge signal output;
a request event conductor to transmit the request signal output of the first controller circuit to the request signal input of the second controller circuit;
an acknowledge event conductor to transmit the acknowledge signal output of the second controller circuit to the acknowledge signal input of the first controller circuit;
a detector component, comprising a filter circuit, to detect a speed mismatch over a selectable period of time to determine a time separation between a first time of arrival of a request event signal assertion on the request signal output and a second time of arrival of an acknowledge event signal assertion on the acknowledge signal output, wherein the selectable period of time is based at least in part on a selectable number of samples; and
a compensator circuit to adjust a supply voltage to the plurality of circuit elements in the data path based on the detected time separation.
2. The system as set forth in claim 1 , wherein the compensator circuit is operable for being initialized using at least one of, a hardware initialization, a software initialization, or an external initialization.
3. The system as set forth in claim 1 , wherein the compensator circuit comprises at least one of, a signal to raise a voltage, a signal to lower a voltage, a signal to select a number of samples.
4. The system as set forth in claim 1 , wherein the detector component comprises at least one of, detecting a two-phase controller event, detecting a four-phase controller event, detecting a synchronous clock event.
5. The system as set forth in claim 1 , wherein the compensator circuit to adjust the voltage comprises adjusting at least one of, a supply voltage, a bias voltage.
6. The system of claim 1 , wherein the compensator circuit lowers the voltage of the first controller circuit when the first time of arrival of a request event signal assertion occurs before the second time of arrival of an acknowledge event signal assertion.
7. The system of claim 1 , wherein the compensator circuit lowers the voltage of the second controller circuit when the second time of arrival of an acknowledge event signal assertion occurs before the first time of arrival of a request event signal assertion.
8. The system of claim 1 , wherein the first pulsed latch enable signal is operable to enable a first level-sensitive latch.
9. The system of claim 1 , wherein the second pulsed latch enable signal is operable to enable a second level-sensitive latch.
10. The system of claim 1 , further comprising a pulse generator that transforms every transition of the first control signal into a pulse operable to enable the first level-sensitive latch.
11. The system of claim 1 , wherein the filter comprises a number of samples that is initialized under external control.
12. The system of claim 11 wherein the number of samples are dynamically varied based at least in part on actual operating conditions.
13. The system of claim 1 , wherein the filter comprises a fixed-length hardware FIFO.