IP Library › Granted Patent US 8,260,449
Granted Patent B2
US 8,260,449 · App. 12/266,276 · Granted Sep 4, 2012

Photolithography systems and associated methods of overlay error correction

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,260,449
App. No.
12/266,276
Granted
Sep 4, 2012
Kind
B2
Abstract

Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for correcting overlay errors in a photolithography system includes measuring a plurality of first overlay errors that individually correspond to a microelectronic substrate in a first batch of microelectronic substrates. The method also includes determining a relationship between the first overlay errors and a first sequence of the microelectronic substrates in the first batch. The method further includes correcting a second overlay error of individual microelectronic substrates in a second batch based on a second sequence of the microelectronic substrates in the second batch and the determined relationship.

Claims (43)

1. A method for correcting overlay errors in a photolithography system, the method comprising:

measuring a plurality of first overlay errors individually corresponding to a microelectronic substrate in a first batch of microelectronic substrates;

determining a relationship between the first overlay errors and a first sequence of the microelectronic substrates in the first batch; and

correcting a second overlay error of individual microelectronic substrates in a second batch based on

a second sequence of the microelectronic substrates in the second batch corresponding to the first sequence of the microelectronic substrates in the first batch such that the correction of the second overlay error of the individual microelectronic substrates in the second batch are based on the measurement of a corresponding microelectronic substrate in the first batch, and

the determined relationship between the first overlay errors and the first sequence of the microelectronic substrates in the first batch.

2. The method of claim 1 wherein measuring a first overlay error includes:

measuring a first overlay error that includes at least one of an X-translation, a Y-translation, a substrate rotation, a substrate orthogonality, a field magnification, an asymmetrical magnification, a field rotation, a field asymmetrical rotation, a substrate expansion along the X-axis, and a substrate expansion along the Y-axis of the individual microelectronic substrates in the first batch;

and wherein determining a relationship includes determining at least one of a linear relationship or a second-order relationship between at least one of the X-translation, the Y-translation, the substrate rotation, the substrate orthogonality, the field magnification, the asymmetrical magnification, the field rotation, the field asymmetrical rotation, the substrate expansion along the X-axis, and the substrate expansion along the Y-axis of the individual microelectronic substrates with respect to the first sequence of microelectronic substrates in the first batch;

and further wherein correcting a second overlay error includes correcting at least one of the X-translation, the Y-translation, the substrate rotation, the substrate orthogonality, the field magnification, the asymmetrical magnification, the field rotation, the field asymmetrical rotation, the substrate expansion along the X-axis, and the substrate expansion along the Y-axis of the individual microelectronic substrates in the second batch based on the determined linear relationship and/or the second-order relationship and the second sequence of the microelectronic substrates in the second batch.

3. The method of claim 1 wherein measuring a first overlay error includes measuring at least one of an X-translation, a Y-translation, a substrate rotation, a substrate orthogonality, a field magnification, an asymmetrical magnification, a field rotation, a field asymmetrical rotation, a substrate expansion along the X-axis, and a substrate expansion along the Y-axis of the individual microelectronic substrates in the first batch.

4. The method of claim 1 wherein determining a relationship includes performing linear and/or second-order regression on the measured overlay errors with respect to the first sequence of microelectronic substrates in the first batch.

5. The method of claim 1 wherein determining a relationship includes determining a substrate-to-substrate variation of the measured overlay errors with respect to the first sequence of microelectronic substrates in the first batch.

6. The method of claim 1 , further comprising determining a first overlay parameter for a first microelectronic substrate in the second batch and a second overlay parameter for a second microelectronic substrate in the second batch based on the second sequence of the microelectronic substrates in the second batch and the determined relationship between the first overlay errors and the first sequence of the microelectronic substrates in the first batch, the first overlay parameter being different than the second overlay parameter.

7. The method of claim 1 , further comprising determining a first overlay parameter for a first microelectronic substrate in the second batch and a second overlay parameter for a second microelectronic substrate in the second batch based on the second sequence of the microelectronic substrates in the second batch and the determined relationship between the first overlay errors and the first sequence of the microelectronic substrates in the first batch, the first overlay parameter being different than the second overlay parameter, and wherein correcting a second overlay error includes individually correcting an overlay error for the first and second microelectronic substrates based on the first and second overlay parameters, respectively.

8. The method of claim 1 wherein determining a relationship includes determining a linear relationship between the first overlay errors and the first sequence, and wherein the method further includes determining a first overlay parameter for a first microelectronic substrate in the second batch and a second overlay parameter for a second microelectronic substrate in the second batch based on the determined linear relationship, and wherein correcting a second overlay error includes individually correcting an overlay error for the first and second microelectronic substrates based on the first and second overlay parameters, respectively.

9. The method of claim 1 wherein determining the relationship includes determining a linear relationship and/or a higher-order relationship of the measured plurality of first overlay errors of the microelectronic substrates in the first batch, and wherein correcting the second overlay error of the microelectronic substrates in the second batch is based on the determined linear relationship and/or the higher-order relationship.

10. A method for correcting overlay errors in a photolithography system, the method comprising:

receiving a set of overlay errors in which individual overlay errors correspond to an individual microelectronic substrate in a set of microelectronic substrates; and

computing a mathematical model based on the overlay errors and a sequence of the microelectronic substrates to correct overlay errors of subsequently processed microelectronic substrates based on overlay errors of respective microelectronic substrates in the set of microelectronic substrates.

11. The method of claim 10 wherein receiving the set of overlay errors includes receiving at least one of an X-translation, a Y-translation, a substrate rotation, a substrate orthogonality, a field magnification, an asymmetrical magnification, a field rotation, a field asymmetrical rotation, a substrate expansion along the X-axis, and a substrate expansion along the Y-axis of the individual microelectronic substrates in a batch.

12. The method of claim 10 wherein the plurality of microelectronic substrates are a first plurality of microelectronic substrates, and wherein the method further comprises

retrieving the mathematical model computed based on the overlay error and the sequence of the first plurality of microelectronic substrates; and

calculating an overlay correction parameter for a microelectronic substrate based on the retrieved mathematical model and a sequence of the microelectronic substrates in a second plurality of microelectronic substrate.

13. The method of claim 10 wherein the plurality of microelectronic substrates are a first plurality of microelectronic substrates, and wherein the set of overlay errors is a first set of overlay errors, and wherein the method further comprises:

receiving a second set of overlay errors of individual microelectronic substrates in a second plurality of microelectronic substrates;

purging the computed mathematical model based on the first set of overlay errors; and

computing a new mathematical model based on the second set of overlay errors and a sequence of the second plurality of microelectronic substrates.

14. The method of claim 10 wherein the plurality of microelectronic substrates are a first plurality of microelectronic substrates, and wherein the set of overlay errors is a first set of overlay errors, and wherein the method further comprises:

receiving a second set of overlay errors of individual microelectronic substrates in a second plurality of microelectronic substrates;

reassimilating the mathematical model based on the second set of overlay errors and a sequence of the second plurality of microelectronic substrates.

15. A method for correcting overlay errors in a photolithography system, the method comprising:

storing a sequence number of a microelectronic substrate in a first set of microelectronic substrates; and

storing a mathematical model of at least one of an X-translation, a Y-translation, a substrate rotation, a substrate orthogonality, a field magnification, an asymmetrical magnification, a field rotation, a field asymmetrical rotation, a substrate expansion along the X-axis, and a substrate expansion along the Y-axis of the individual microelectronic substrates with respect to the sequence number; and

correcting at least one overlay error of a microelectronic substrate in a second set of microelectronic substrates having the same sequence number as the microelectronic substrate in the first set of microelectronic substrates using the mathematical model.

16. The method of claim 15 wherein the storing the sequence number includes storing discrete integers identifying the individual microelectronic substrates in the set.

17. The method of claim 15 wherein storing the mathematical model comprises storing the mathematical model as a linear polynomial or a second-order polynomial.

18. A method for correcting overlay errors in a photolithography system, the method comprising:

processing a first batch of microelectronic substrates in a first sequence;

measuring a plurality of first overlay errors corresponding to respective microelectronic substrates in the first batch; and

correcting a second overlay error of each microelectronic substrates in a second batch using a substrate-to-substrate mathematical model based on the first overlay error of the respective microelectronic substrate in the first batch.

19. The method of claim 18 wherein correcting the second overlay error of each microelectronic substrate includes substrate-to-substrate correction of processing overlay errors of the microelectronic substrates in the second batch.

20. The method of claim 18 wherein measuring the plurality of first overlay errors includes measuring an overlay error of a first microelectronic substrate and a second microelectronic substrate in the first batch, and wherein correcting the second overlay error includes correcting a processing error of a first microelectronic substrate in the second batch based on the measurement of the overlay error of the first microelectronic substrate in the first batch and also correcting processing of a second microelectronic substrate in the second batch based on the measurement of the overlay error of the second microelectronic substrate in the first batch.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2008
From: CHUNG, WOONG JAE
To: MICRON TECHNOLOGY, INC.
Reel/Frame 021798/0085 →
Continuity (1)
Related Publication 20100112467A1 · May 6, 2010