Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence
By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.
1. A method, comprising:
forming a spacer element comprising an etch stop layer portion and a spacer layer portion at sidewalls of a gate electrode structure of a transistor by forming an etch stop layer and a spacer layer and performing an anisotropic etch process using said etch stop layer as an etch stop;
forming first drain and source areas of drain and source regions of said transistor by using said sidewall spacer element as a first implantation mask;
reducing a width of said spacer element to a first reduced width by removing only a first portion of said spacer layer portion of said spacer element; and
forming an intermediate portion of said drain and source regions by using the spacer element with said first reduced width as a second implantation mask.
2. The method of claim 1 , further comprising forming drain and source extension regions of said drain and source regions prior to forming said sidewall spacer element.
3. The method of claim 1 , further comprising forming a metal silicide in said drain and source regions on the basis of the spacer element with said first reduced width.
4. The method of claim 1 , wherein removing only said first portion of said spacer layer portion of said spacer element comprises performing a wet chemical etch process.
5. The method of claim 4 , wherein performing said wet chemical etch process comprises using hydrofluoric acid (HF) diluted in ethylene glycol.
6. The method of claim 1 , further comprising forming a stress-inducing dielectric material above said spacer element with said first reduced width.
7. The method of claim 1 , wherein said spacer layer is comprised of a nitrogen-containing material and said etch stop layer comprises silicon dioxide.
8. The method of claim 1 , wherein said spacer layer is comprised of silicon dioxide and said etch stop layer comprises a nitrogen-containing material.
9. The method of claim 1 , further comprising reducing said width of said spacer element to a second reduced width by removing only a second portion of said spacer layer portion of said spacer element with said first reduced width.
10. The method of claim 9 , further comprising forming metal silicide regions in said drain and source regions on the basis of said spacer element with the second reduced width.
11. The method of claim 1 , further comprising forming a second sidewall spacer element at sidewalls of a second gate electrode structure of a second transistor and said sidewall spacer element in a common process sequence and removing a portion of said second sidewall spacer element so as to form said second sidewall spacer element with a reduced width that differs from said first reduced width of said sidewall spacer element.
12. The method of claim 11 , wherein removing a portion of said second sidewall spacer element comprises implanting a dopant species into said second transistor while covering said transistor with an implantation mask and performing an etch process in the presence of said implantation mask.
13. The method of claim 1 , further comprising forming offset spacers on said sidewalls of said gate electrode structure prior to forming said spacer element.
14. A method, comprising:
forming a spacer layer having a substantially homogenous material composition above a transistor;
etching said spacer layer to form a sidewall spacer element at a sidewall of a gate electrode structure of said transistor, wherein said sidewall spacer element comprises a first portion and a second portion, said first and second portions each comprising material of said spacer layer;
performing a first implantation process to form a first portion of drain and source regions of said transistor;
reducing a width of said sidewall spacer element by removing only said first portion of said sidewall spacer element and leaving said second portion; and
after reducing said width, performing a second implantation process to form a second portion of said drain and source regions of said transistor.
15. The method of claim 14 , wherein reducing a width of said sidewall spacer element comprises performing a wet chemical etch process.
16. The method of claim 15 , wherein the wet chemical etch process is performed on the basis of hydrofluoric acid and ethylene glycol.
17. The method of claim 14 , further comprising forming drain and source extension regions prior to forming said spacer layer.
18. The method of claim 17 , further comprising forming metal silicide regions on the basis of said sidewall spacer element having said reduced width.
19. The method of claim 14 , further comprising further reducing the width of said sidewall spacer element after performing said second implantation process.
20. The method of claim 14 , further comprising forming an offset spacer on said sidewall of said gate electrode structure and forming an etch stop layer on said offset spacer prior to forming said spacer element.
21. A method, comprising:
determining a first target width of a spacer element for defining deep drain and source regions of a specified type of transistor;
determining a second target width of a spacer element for defining intermediate drain and source regions of said specified type of transistor;
forming an etch stop layer above one or more substrates, each of said one or more substrates including said specified type of transistor;
forming a spacer layer on said etch stop layer on the basis of said first target width;
etching said spacer layer to form said spacer element by using said etch stop layer as an etch stop, said spacer element comprising an etch stop layer portion and a spacer layer portion;
forming said deep drain and source regions;
reducing a width of said spacer element on the basis of said second target width by removing only a first portion of said spacer layer portion of said spacer element; and
forming said intermediate drain and source regions.
22. The method of claim 21 , further comprising determining a third target width of said spacer element, wherein said third target width is less than said second target width, and adjusting a width of said spacer element on the basis of said third target width by removing only a second portion of said spacer layer portion of said spacer element and forming a stressed dielectric material above said one or more substrates.
23. The method of claim 22 , wherein a width of said spacer element on the basis of said third target width is adjusted after forming metal silicide regions in said drain and source regions of said specified type of transistor.
24. The method of claim 21 , further comprising forming offset sidewall spacers on said specified type of transistor prior to forming said etch stop layer.