Memory and method for dissipation caused by current leakage
Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.
1. A memory, comprising:
a current generator, generating a control current;
at least one bit line, coupled or dis-coupled to the current generator by a bit line selector;
at least one memory cell, coupled to the bit line and comprising a transistor and a storage element that are coupled in series, wherein the transistor is turned on or off by a word line signal and the storage element is switched between a plurality of states according to current flowing therethrough; and
a current leakage suppressor, comprising:
an inverter, having an input terminal receiving an enable signal and an output terminal outputting an opposite phase signal of the enable signal;
a first transmission gate, coupled between a ground and the power supply input terminal of the current source, and having a first control terminal and a second control terminal coupled to the input and output terminals of the inverter, respectively; and
a second transmission gate, coupled between the voltage source and the power supply input terminal of the current source, and having a first control terminal and a second control terminal coupled to the output terminal and the input terminal of the inverter, respectively.
2. The memory as claimed in claim 1 , wherein the transistor comprises a first terminal and a second terminal and the first terminal is coupled to the bit line.
3. The memory as claimed in claim 2 , wherein the second terminal of the transistor is coupled to the ground.
4. The memory as claimed in claim 3 , wherein the current leakage suppressor couples the current generator to a voltage source or the ground.
5. The memory as claimed in claim 4 , wherein the current leakage suppressor is operable to couple a power supply input terminal of the current generator to the voltage source when the memory is being accessed, and couple the power supply input terminal of the current generator to the ground when the memory is not being accessed.
6. A memory, comprising:
a current generator, generating a control current;
at least one bit line, coupled or dis-coupled to the current generator by a bit line selector;
at least one memory cell, coupled to the bit line and comprising a transistor and a storage element that are coupled in series, wherein the transistor is turned on or off by a word line signal and the storage element is switched between a plurality of states according to current flowing therethrough; and
a current leakage suppressor, coupling an output terminal of the current generator to a ground when the memory is not being accessed,
wherein the current leakage suppressor comprises a transistor comprising a first terminal, a second terminal and a control terminal coupled to the output terminal of the current generator, the ground and an enable signal, respectively, wherein the enable signal enables the transistor when the memory is not being accessed and disables the transistor when the memory is being accessed.
7. The memory as claimed in claim 1 , wherein the storage element is phase change storage element.
8. The memory as claimed in claim 6 , wherein the transistor comprises a first terminal and a second terminal and the first terminal is coupled to the bit line.
9. The memory as claimed in claim 8 , wherein the second terminal of the transistor is coupled to the ground.
10. The memory as claimed in claim 9 , wherein the current leakage suppressor couples the current generator to a voltage source or the ground.
11. The memory as claimed in claim 10 , wherein the current leakage suppressor is operable to couple a power supply input terminal of the current generator to the voltage source when the memory is being accessed, and couple the power supply input terminal of the current generator to the ground when the memory is not being accessed.
12. The memory as claimed in claim 6 , wherein the storage element is phase change storage element.